This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8305-Q1: device gate disabled and in sleep mode - what are the voltage levels I should expect to see?

Part Number: DRV8305-Q1

Team,

Can you please help answer customer's question:

If we disable EN_GATE and WAKE of the device (device gate disabled and in sleep mode) what are the voltage level at GHA, SHA, GHB, SHB, and GHC, SHC?

What I measured are:

V_GHA=0.005V

V_SHA=0.005V

V_GHB=0.262V

V_SHB=0.263V

V_GNC=0.262V

V_SHC=0.263V

Thanks

Viktorija

  • Hey Viktorija,

    As described in the standby mode section in the datasheet, "the major gate driver blocks are disabled, but the passive gate pulldowns are still active to maintain the external MOSFETs in their high-impedance state." In addition there should be a sort of weak pull down that's trying to take current out of the gate. As such, most steady state conditions we expect V_SHx = V_GHx, and that's it. Maybe there are cases where V_GHx are millivolts higher than V_SHx, but it shouldn't be for long. 

    In this case, the SHx node is floating. So measuring a floating node in reference to some GND that is through a very high impedance path is not very helpful. So when I see the >200mV on the node and that it is different from another node, I don't have a concern. I'm only looking if V_SHx = V_GHx. And explaining why one leg measures >200mV and why another measure 0V, is not helpful either. Maybe you could get into Q = CV theory with the FETs, what the motor was doing before enable went low, and where the lowest parasitic path in the layout would allow for discharge, but again, I don't see any benefit.

    To expand on why it is considered floating, the motor phase wire is considered a high impedance path, and both the high and low side FETs in that leg of the power stage are considered "off" so they are also a high impedance path. The lowest impedance path within the DRVx is the path between SHx and GHx, which we already talked about, so every other path is higher impedance path where current will not flow.

    Best,

    -Cole