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DRV8873S-Q1EVM: SPI transactions says 16-bits in user manual, but are two 8-bit in evaluation code

Part Number: DRV8873S-Q1EVM
Other Parts Discussed in Thread: DRV8873-Q1, DRV8873

Hi. 

I noticed in the evaluation software that SPI transactions are being done as two 8-bit transactions (drv8873x-q1.c, function drv_8873xq1_readRegister).  I was expecting one 16-bit transaction, as detailed in the user manual (drv8873-q1.pdf, section 7.5.1.2).

Why are these different?

Best regards

Erek Burek

Nikola Motors

  • Erek,

    It is 8-bits of command and 8-bits of data.  Each register in the device is only 8-bits.  This is for a WRITE.

    For a read, it is 8-bits of status and 8-bits of register data.  

    I can't see the pictures you embedded.  Please try to use the "paperclip" icon above to attach images.

  • Hi Ryan,

    Thank you for reply and explanation.

    The DRV8873 user manual makes it seem like SPI transitions are done as a 16-bit word, and not as two transitions of 8-bit bytes.  It is not very clear to me, nor any of my colleagues, that SPI transitions are done as two transitions of 8-bit bytes from reading the user manual.

    Section 7.5.1.1 SPI Format

    • "SDI input data word is 16 bits long"
    • "SDO output-data word is 16 bits long"

    Section 7.5.1.2 SPI for a Single Slave Device

    • "The SPI input-data (SDI) word consists of a 16-bit word"
    • "If the data word sent to SDI pin is less than 16 bits or more than 16 bits, a frame error occurs and the data
      word is ignored."

    Why is the user manual describing a 16-bit word for the SDI and SDO?

    Best regards

    Erek

  • Erek,

    Just to be clear, when you say "user manual", you are referring to the datasheet?  We do have a user manual for the software and EVM, so just want to make sure we are on the same page.  

    Do you have an EVM  seeing only 8-bits sent within a SPI frame (nSCS low)?  This should not be the case.  It should look like figure 22 in the datasheet.  8-bits of command, 8-bits of data.  

    I believe the datasheet to be correct.  Within a single SPI frame, 16 bits of data are sent in order for it to be valid.

  • Hi Ryan,

    I am referring to document "drv8873-q1.pdf" "DRV8873-Q1 Automotive H-Bridge Motor Driver".

    I am getting a total of 16-bits from DRV8873 device, but am getting it by doing two 8-bits transfers.  

    In the "drv8873x-1q.c" source code provided (below) for the EVM for the MSP430 to communicate with the DRV8873 it actually does two 8-bit data transfers. Transmits 8-bits, then waits for transmit complete, then  receives 8-bits, then transmits another 8-bits, then waits for another transmit complete, then receives another 8-bits.  This is not a 16-bit transactions.  This is two 8-bit transactions.  A 16-bit transaction would have been to transmit 16-bits, wait for transmit complete, receive 16-bits.  This is what was expected from reading the pdf on DRV8873.  The DRV8873 does not do within a single SPI frame, 16-bits of data are sent in order for it to be valid. You can actually receive a valid upper 8-bits of data by only transmitting 8-bits of data.

    The data sheet really does not seem to be correct, respectfully.

    uint16_t drv8873xq1_readRegister(uint8_t address)
    {
    volatile uint16_t reg_value = 0;
    volatile uint8_t dataMSB = 0;
    volatile uint8_t dataLSB = 0;

    reg_value |= SPI_RW_BIT_MASK; /*Set R/W bit*/
    reg_value |= ((address << SPI_ADDRESS_POS) & SPI_ADDRESS_MASK); /* Configure register address value*/
    //reg_value |= ((data << SPI_DATA_POS) & SPI_DATA_MASK); /*Adding data value */

    P2OUT &= ~nSCS;//SPI set

    while (!(IFG2 & UCB0TXIFG)); /* USCI_B0 TX buffer ready*/
    UCB0TXBUF = (uint8_t)((reg_value >>8) & 0xFF); /* Transmit the Address(MSB Byte)*/

    while(UCB0STAT & SPI_BUSY_FLAG)
    {
    ; /* Wait till Transmission is complete*/
    }
    dataMSB = UCB0RXBUF; /* Recieve the First byte of data, MSB byte*/

    UCB0TXBUF = 0x00; /* Transmit Second byte*/
    while(UCB0STAT & SPI_BUSY_FLAG)
    {
    ; /* Wait till Transmission is complete*/
    }
    dataLSB = UCB0RXBUF & 0xFF; /* Recieve the Second byte,LSB byte*/

    P2OUT |= nSCS; //SPI Reset
    _delay_cycles(10);

    reg_value = ((((dataMSB<<8) | dataLSB) & SPI_DATA_MASK)>>SPI_DATA_POS); /* complete data */

    return (reg_value);
    }

  • Erek,

    Please give me 24 hours to investigate this with some team members and I will post again.

  • Erek,

    It is a limitation on the MSP430 that is on the evaluation board.

    The MSP430 SPI frame width is one byte.  Hence, a two byte back-to-back transaction was done to deal with the required 16-bits in a single frame and clock was "stretched" between two bytes.  

    As the communication is synchronous, it does not affect the data. 

    If you have a host processor which can support 16-bit SPI frame, then a single transaction can be done per our datasheet.

    I hope this alleviates your concerns.  The datasheet is correct by all accounts on our side.