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DRV8860: Design checks

Furkan Fehmi Sefiloglu
Expert 3118 points
Part Number: DRV8860
Other Parts Discussed in Thread: ISO7742, ISO7741

Hi Team, 

Can you please advise with request:

"

1- We are using 2 pieces of DRV8860PWP on the same card. We took the control ends of the DVR8860s directly to the processor by making them parallel instead of daisy chain. In other words, DIN-DOUT-CLK-LATCH inserts were used jointly for both. We will check the Fault and Enable ends separately. We planned that the DRV8860 we wanted to drive would be active with ENABLE and the other DRV8860 would passive with its ENABLE tip and communicate in that way. Is such a study appropriate?

2- Do the outputs of the DRV8860, which is disabled in the way I mentioned above, keep their status? For example, what happens if the DRV8860, which is currently driving a solenoid, is passive?

3- There is an information that the DOUT tip DRV8860 is internally pulled up to 5.7V in one of the tables in the datasheet. When you look at the diagram I sent, we isolated the processor side with a DRV8860 using ISO7741 and ISO7742. We fed the DRV8860 side of ISO7741 and ISO7742 with 5V. As you can see in the diagram, we tried to stabilize the DOUT voltage to 5V with the zener acting like a TVS. What is your comment and suggestion about the suitability of this structure?

4- nFAULT ends are defined as open drain. We pulled the nFAULT ends to 5V, which is the voltage level of ISO7741 and ISO7742 as pull up. I don't think it will be a problem, but can you comment if it is appropriate?

"

Thanks in advance

Best Regards

Furkan Sefiloglu 

  • 0
    TI__Guru 56650 points

    Furkan,

    1. I think two DOUT pins could fight each other. So, DOUT pin needs to be separated. I also assume the two outputs are not connected together.

    2. I think you can set one device active and another one is inactive if the two output are not connected together.

    3. The block diagram was not shown here. A resistor divider on DOUT may works. The Zener could have a higher current and higher cost.

    4.Yes. Since nFault is open drain output, pulling nFault to 5V through a resistor is good to me.

  • 0
    Prodigy 30 points

    Dear Furkan, Dear Wang

    Thank you for your interest and help. The custermer who asked these questions to Mr. Furkan is us.

    I decided to change the interface from parallel connection to daisy chain as decribed in datasheet. So some of the problems are eliminated.

    But there is an other problem about ENABLE pin. If you look at the pin functions table on page 4 in the datasheet you will see a description about ENABLE pin. The description is that "Logic high to enable outputs, logic low to disable outputs. Internal logic and registers can be read and written to when ENABLE is logic low. Internal pulldown."

    The new problem is ; if I want to read or write a register (according to the enable pin description) I must set the ENABLE pin to logic low and make the reading or writing. But if the ENABLE pin is logic low the outputs become disabled. How can I save the last states of the outputs when I want to read/write the registers?

    There is no any other information in the serial communication waveforms about the enable pin.

    Saving the last states of the outputs is very critical for our application. What do you think about this?

    Regards.

    Ozan

  • 0 in reply to Ozan AKC
    TI__Guru 56650 points

    Ozan，

    Internal logic and registers should be read and written to when ENABLE is in both logic high and logic low.

  • 0 in reply to Wang5577
    Prodigy 30 points

    Wang,

    Thank you for your answer.

    In this case, can I connect the ENABLE pin directly to logic high? We do not need to disable the outputs.

  • 0 in reply to Ozan AKC
    TI__Guru 56650 points

    Ozan,

    You can keep ENABLE pin high while doing the serial interface communication.

  • 0 in reply to Wang5577
    Prodigy 30 points

    Wang,

    Thank you for your help. Regards

    Ozan