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DRV8353: Gate drive breaking during normal operation

Part Number: DRV8353
Other Parts Discussed in Thread: CSD18531Q5A, TIDA-010056

This component has been breaking anytime interact with it, really. I'm attaching the schematic and the SPI code, along with some screenshots of gate drive behavior. At this point, we have no idea what's going on. The part has broken or underperformed for what we perceive to be the following reasons:

- We spun our motor by hand when the system wasn't powered on, and the gate drive died.
- We used the default settings, and the gate drive died. (Why are the default settings so strong they can damage the gate drive?)
- We used hand-calculated IDRIVE settings for our FETs, resulting in underperformance and incredibly long switching time (2-5 microseconds). This nagged us repeatedly until we just raised the current by a fair amount more than the math said we should, and then everything looked clean.
- Despite the part datasheet claiming to correct for shoot-through and dv/dt turnon, we've seen clear dv/dt turn-on activity on the oscilloscope before.
- We ran the system with our motor and flywheel, applying a slowly increasing PWM signal on 1x mode, and the chip arbitrarily destroyed its own gate drive with no sign of why. The signals were clear, smooth, and not ringing on the scope.

This part either is very unreliable, or we are doing something extremely wrong. If it's the latter, we need to know what that is. Is the DRV8350S more robust than the DRV8353S? We would be fine substituting a part.

Our application is in industrial machinery. We really can't use a part so fragile that it damages itself if someone spins a motor by hand, for example. Either we need a way to protect it from itself, or we need some other component that is much more rugged. We have 48V batteries as a power source, and we need the drive to be able to run a BLDC motor using up to 50A continuous and 100A peak current.

Please help? This is a high side and low side gate pair. 

Here's our motor drive schematic.

And here are our register settings. 

Driver Control: 0x14C0

Gate Drive Current High Side: 0x1B73

Gate Drive Current Low Side: 0x2353

OCP Control: 0x2934

CSA Control: 0x32C0

We're working on 1x mode right now so that we can do controlled testing without having to program our own commutation yet.

Layout:

  • Hi Alcor,

    I don't have an experience with DRV8353 but just a few things that come to my mind.

    Default settings of gate currents are probably much too high for most of designs.

    IDRIVEP_HS = 450mA what gives switching time around 50ns, it may be still too fast for your layout ie. stray inductances

    between LS Mosfet Source and GND. There is quite high inductance of sense resistor, trace between that resistor and LS Mosfet source

    and inductance of Mosfet source itself (quite high for D2PAK).

    I would be cautious about negative spikes on LS Mosfet gate and source during LS Mosfet body diode recovery.

    Some solution for that spike can be strong pull down function of DRV8353.

    Could you zoom an area of LS Mosfet gate ringing when HS Mosfet is turning ON. Oscilloscope with bandwidth at least 60-100MHz

    needed (BW filter turned off, probe set to 10x and probe ground spring needed).

    IDRIVEP_LS might by slightly too high as well.

    Mosfet gate traces look very thin, that plus lack of continuous ground plane underneath can give lots of stray inductance and troubles.

    Four layer (or more) PCB with solid ground plane would give better thermal performance and could limit problems with stray inductances and

    current return paths.

    Best Regards,

    Grzegorz

  • Hello Alcor,

    There's a lot to unpack here. Let me get back to you tomorrow with a more thorough answer.

    There's a couple of things that stick out to me on first glance:

    • No indication of what might be damaged on the DRV
      • (VGLS short to GND? GLx short to GND? GHx to VCP short?)
    • No waveforms supporting location of damage
    • Two layer design and no indication about design rules or manufacturing
      • (3oz pour?)
    • No high voltage and current operation mitigation circuits
      • TVS, RC snubbers, gate resistors, external GD cap, HS source to LS drain caps
    • Shared VDRAIN and VM trace
      • where a kelvin connection for VDRAIN is needed and makes VDS sensing inefficient
    • No technical elaboration for "spinning motor by hand"
      • E.g. What's Ke? how BEMF is generated? How does this value compare to abs. max of the DRV?
    • GND and "PGND" split but I can't seem to find how they connect
      • We recommend all grounds be connected under device in datasheet and common GND as the preferred layout style.
    • Not a lot of GND stitching vias
    • Sounds like you checked IDRIVE, which is very good,
      • it can save 90% of "DRV is blowing up" cases by reducing the current. If things are still being damaged at this point, by checking waveforms, layout is the next suspect in line.

    Here's a 54-V, 1.5 kW, >99% Efficient, 70x69 mm2 power stage reference design for 3-phase BLDC drives reference design for you to compare to https://www.ti.com/tool/TIDA-010056

    It might take a bit less current but you'll see a lot of differences in design, explained in the design document, that I don't think you have considered. Feel free to correct me if I'm wrong.

    Best,

    -Cole

  • I should clarify more.

    I'm using a 4-layer design, but I just posted the top and bottom layer pictures so you could see the copper routing layout. Here are the two internal layers. 

    Layer 2, with the two ground planes.

    Layer 3, power planes.

    Here are answers to your questions.

    • No indication of what might be damaged on the DRV
      • Specifically, what is happening to the DRV is that it's registering faults for low Vcp and Vgls, and it's shorting Vm to ground. This seems to be consistent with other forum posts that suggest the gate drive is damaged.
    • No waveforms supporting location of damage
      • Yes, this is one of our issues. We haven't managed to catch the waveforms of damage, which is confusing us, because to me this error seems like it's coming out of absolute nowhere.
    • Two layer design and no indication about design rules or manufacturing
      • (3oz pour?)
      • See above info about our design. It's a 4-layer board with a big ground plane and ground pours on the top and bottom. 
      • We use 2 oz copper.
    • No high voltage and current operation mitigation circuits
      • TVS, RC snubbers, gate resistors, external GD cap, HS source to LS drain caps
      • Your eval board doesn't have these. I thought that we wouldn't need extra peripherals, either. What should we be putting on, that didn't show up in your application and eval circuits? Also, I thought gate drive resistors were discouraged because it caused issues with IDRIVE. Can you explain gate-drain caps? What will those do for us? Can you explain these suggestions, please?
    • Shared VDRAIN and VM trace
      • where a kelvin connection for VDRAIN is needed and makes VDS sensing inefficient
      • Oh, that might be a big deal for us -- thank you. We were getting odd VDS readings in that the chip would claim that current spikes were there that we could see were solidly not there on the current sense amp outputs.
    • No technical elaboration for "spinning motor by hand"
      • E.g. What's Ke? how BEMF is generated? How does this value compare to abs. max of the DRV?
      • We don't know the details here. Essentially, we have a BLDC connected to a big aluminum flywheel, and we spun the wheel by hand, rotating the motor shaft. That was it. I saw somewhere on the forums that this might cause damage?
    • GND and "PGND" split but I can't seem to find how they connect
      • We recommend all grounds be connected under device in datasheet and common GND as the preferred layout style.
      • GND and PGND connect here:

    • Not a lot of GND stitching vias
      • Where would you want more? There are stitching vias all over. All those vias you see on the big ground pours on the top layer, those are stitching vias. Maybe we haven't placed some in the right place? But we have a lot.
    • Sounds like you checked IDRIVE, which is very good,
      • it can save 90% of "DRV is blowing up" cases by reducing the current. If things are still being damaged at this point, by checking waveforms, layout is the next suspect in line.
      • Yeah, we meticulously did the math for IDRIVE, so it surely isn't that. That said, when we did the math for about 300 ns, we got in the ballpark of 300mA drive current. It takes double that to reach 500ns. I'm a bit confused why. It might be that the datasheets for the FETs are optimistic, though, and that there's just more capacitance on the FET than we think.

    Thank you so much for your help! I put comments in blue because I felt it was easy to read.

  • Hi Alcor,

    Such long switching time is very suspicious, I use CSD18531Q5A  with Qgd of 5.9nC at Vds = 30V, at 50V Qgd would be (it's just my guess) 50/30 x 5.9 = 9.83nC.

    For a gate current of 150mA it should be 9.83/0.15 = 65.5ns but in reality it is around 80ns, so pretty close.

    I would check those Mosfets outside the board using some other gate driver (function generator with resistor may be a good solution).

    As a switching time I mean time for an output voltage to go from 10% to 90% or from  90% down to 10%.

    Regards,

    Grzegorz

  • Hello Alcor,

    My Opening Thoughts:

    Thanks for the response. I'll pick out a few that I want to comment on.

    • No high voltage and current operation mitigation circuits
      • TVS, RC snubbers, gate resistors, external GD cap, HS source to LS drain caps
      • Your eval board doesn't have these. I thought that we wouldn't need extra peripherals, either. What should we be putting on, that didn't show up in your application and eval circuits? Also, I thought gate drive resistors were discouraged because it caused issues with IDRIVE. Can you explain gate-drain caps? What will those do for us? Can you explain these suggestions, please?
        • The DRV8353RSEVM is rated for 15A peak (section 2.1 of user's guide), which is a lot less than 50A. What most people don't understand is that the step from 720W to 1kW (or 2.4kW in your case) is major step in high power design. As such, a good enough layout would not require all of the mitigation circuits I've mentioned but, just like EMI, its still a smart idea to have footprints for these circuits that could be added later and if the design isn't testing up to specifications. I'll talk more on the technical detail later but just know that we have this subject planned on our collateral roadmap, and hope to have it more readily available in the future.
        • If you look to the TI design I referenced earlier, it has some of the circuits I've mentioned
    • No technical elaboration for "spinning motor by hand"
      • E.g. What's Ke? how BEMF is generated? How does this value compare to abs. max of the DRV?
      • We don't know the details here. Essentially, we have a BLDC connected to a big aluminum flywheel, and we spun the wheel by hand, rotating the motor shaft. That was it. I saw somewhere on the forums that this might cause damage?
        • Its a good thing to test on the system. Imagine some sort of external source (like wind or an human operator) who decides the to move the rotor by hand. The rotor passes by unexcited motor stator coils, and Back Electromotive Force (BEMF) is generated. Depending on the BEMF constant, Ke, the motor will generate large enough voltage, and current, that can destroy the motor driver and surrounding parts.
        • The problem becomes when to account for this. If the device is on and in an idle state, some users decide to keep the low side or high side FETs energized in brake state that will cause the energy decay within the motor coils, instead of outside in the system. If the system is powered off and someone moves the rotor... well that's a hard one, most just rely on the passive components to do the job (like a TVS or similar) to divert the energy away from the motor driver.
    • GND and "PGND" split but I can't seem to find how they connect
      • We recommend all grounds be connected under device in datasheet and common GND as the preferred layout style.
      • GND and PGND connect here:
        • Well that explains quite a bit. Don't think I see R25 or C41 on the schematic you provided, and I hope you don't have your GND's capacitively coupled.
        • Our Layout guidelines show a ground example in section 2.1 https://www.ti.com/lit/an/slva959a/slva959a.pdf
        • Explicitly, the split GND, as you have done, is only recommended when the DRV is in the path of the motor current. Otherwise, common grounding is always preferred and will result in better performance. Correct me if I'm wrong but your path of current is pretty clearly not near the DRV
        • Take a look at figures 26-29 in the TIDA-010056 design guide. This design is similar enough to yours, and its using common grounding and waveforms look pretty good

    • Not a lot of GND stitching vias
      • Where would you want more? There are stitching vias all over. All those vias you see on the big ground pours on the top layer, those are stitching vias. Maybe we haven't placed some in the right place? But we have a lot.
      • Looks like you're using altium. You can go into tools -> Via Stiching and select the whole board to stitch the GND planes together, so you don't have to do it by hand. You can use the EVM hardware files as reference for the specs of the array.
      • But in general, its clear the current needs to go centimeters away to find a via nearby to move to another layer on the right hand side of your board (where that GND connector is). Even a lot of your electrolytic bulk capacitors don't have vias nearby, it solely depends on the singular through-hole GND lead to connected between inner and bottom layers.

    Other Things I'm noticing:

    • Surprised to see that you didn't pour GND on layer 3, there's a lot of empty space that can utilized . I know power is for power and GND is for GND but if you keep some spacing tolerances between GND and power, then there's really no problems with doing it this way
    • There's not a lot of voltage ratings on these caps but I saw a couple that are showing 50V
      • As a reminder, small capacitors are supposed to help during high frequency transients so the voltage rating still matters. But all ceramics have bad capacitance voltage derating. We recommend 2x voltage rating to start (1.5x if there is absolutely no space). See example below that shows 1/2 derating at the voltage rating. See this picture for a manufactures derating
      • Applying this To every component is recommended
      • Highly recommended to not use two capacitors in place of 1 as well. Can introduce voltage instability on rails that depend on the output capacitance
    • Looks like you have a lot of decoupling capcaitance focused on VM where they should be closer to drains of the high side FETs. Remember, the VM will only take a transient of an amp at most where the VDRAIN or drains of the High side FETs, are the ones doing 50A_RMS.
    • Agreed with Grzegorz, your gate and source traces look like 10mil (just guessing) and you're sourcing and sinking current from the gates that way. We want thicker traces than just the width of the pin here. Thicker traces, less inductance.
    • Looks like AGND and PGND pins are separate at DRV. They should be tied together, even under the power pad.
      • Small hint, GND pins that are near other pins tell you about what part of the circuit relates to the GND pin on a silicon die level within the package. So AGND being near VREF shows that the GND loop for the output capacitor between VREF and AGND should be small. You can repeat the logic through the device when deciding where to put the decoupling caps (DGND and DVDD, etc). This is almost true for any semiconductor you find.
    • It looks like you're routing the motor phases through 100mil header connection on J2? 2.7 kW need thick guage wire soldered directly into a board connector, like you did for GND

    Registering faults for low Vcp and Vgls, and it's shorting Vm to ground

    Yeah, usually one will fail but if both are failing, I would consider that to be catastrophic. I'd be curious about the waveforms still. I'll have to comment on the high power techniques tomrrow.

    Best,

    -Cole

  • Hi Alcor,

    Max. slew rate for TVS1400DRVR (devices protecting Mosfet gates in your design) is 0.7-2.5 V/us depending on temperature.

    It is possible that they slow down rising of voltage on Mosfet gates.

    Regards,

    Grzegorz

  • We've removed those diodes for that reason. All the things I've mentioned are without the diodes.

  • Hey Alcor,

    Thought this was the case, thanks for confirming

    As you probably noticed, didn't get to the rest of the high power design techniques. Hope to address before the end of the week.

    Best,

    -Cole

  • Hi Cole,

    Any time for those techniques?

    Thanks,

    Alcor

  • Hello Alcor,

    Wish I had more time but yes, I should be finished with the response tomorrow.

    Best,

    -Cole

  • Hello Alcor,

    Let's go for it. It’s a lot.

    Intro into our high power design philosophy:

    First, it’s inevitable that your high power design (48V, >500W) will have some sort of voltage or current spiking. There's parasitic inductance and capacitance all over the board. We can't avoid it, only suppress it or mitigate it.

    This is the same exact mindset we share with EMI. Should I put a ferrite bead there; should I put a gate resistor there? Where are my GND loops on my signal chain decoupling caps, where are my GND loops on my gate drive current path? Should I use shielded components; should I use a higher voltage rating components? Hopefully this makes sense.

    Simply put, the difference between 5A and 50A means magnetic fields are 10x stronger and the voltage generated by di/dt are 10x larger. It is even worse if the ringing lines up with some self-resonant frequency of all the Ls and Cs on the board.

    Gate Current and Gate resistors

    Simply put, introducing more current at the gate of the FET means the channel will open up more quickly and the equivalent voltage on the Gate and VDS will rise more quickly. Faster the slew rate on signals, the more high frequency content they contain which means they will ring at higher amplitude (as a result of higher di/dt). Flipping the logic, less gate current means less voltage spiking will occur. This is a tactic you’ve seen us use a lot of E2E to see if these kinds of problems can be mitigated.

    In the case of the competitors, it’s adding a gate resistor (3-15 ohms) and for smart gate drive technology, it’s changing the source and sink current (IDRIVE), or both.

    I agree that it makes a lot of stuff worse: thermals, EMI (in some cases), effective applied PWM duty cycle, etc. Without other options, most customers will have to make the tradeoff to get their existing system to work (as fixing the problems mentioned in the first section require board redesigns).

    Blue wiring in some these other suggested components are just bandaids that prove that they will help in the long run as it is difficult to go to production with handwiring components to every product (especially when they add more parasitics which could make it worse).

    Small mention to C_GD caps, they essentially make the equivalent Q_GD larger (caps in parallel add) so it takes more charge to turn on the FETs and get through the FETs.

    RC Snubbers

    This TI Design I keep mentioning has RC snubbers on the lowside and high side FETs. Specifically, R1 & C13, C16 & R14, R2 & C14, C17 &15, R3 & C15, and C18 & R16 are the RC snubbers. That’s 12 components. The design guide also talks about the wattage rating of components (namely, 1/3*C*V^2*f_sw = P) and the blog below shows you how to calculate the components.

    https://e2e.ti.com/blogs_/b/powerhouse/posts/calculate-an-r-c-snubber-in-seven-steps

    The “too long, didn’t read” summary for the blog shows that finding the optimal RC values require the board to be built, as they depend on parasitics of the board. Then the board is tested by swapping out the R and C and an equation is used to get the optimal value.

    Also note, RC snubbers do a really good job suppressing after the initial spike, as the energy needs some time store into the capacitor. This means, its good for “settling time” but not the initial “overshoot”.

    Decoupling Capacitors, and Bulk caps

    Other engineers have said quite a bit about this one, so you can find more info elsewhere.

    Decoupling capacitors have the primary purpose to provide charge into a system so the main power supply doesn’t have to. We know that small valued capacitors can be emptied and filled with charge relatively quickly, where larger valued capacitors can store a lot of energy, but not react as quickly. This is why you see 10uF in combination with 100nF capacitors placed on power supplies. Because the cap values can provide some charge quickly and a lot of charge over time, it helps with ringing and the initial spikes for the design. There’s some more nuance as the smaller caps can be made out of different material and construction geometry to allow less parasitics in the path of charge, but I’ll skip over the details.

    Now, the caps are supposed to supply current (charge over time or C*V/t) which must travel through traces to the drain of the high side FETs, assuming the bulk capacitors are connected from the HS Drain to GND (bottom of sense resistors). This this case, we want the path between the caps and the HS Drain to be short and thick, and we want a lot of GND stitching vias to carry more current (as opposite charge needs to build up on the anode of the cap) near the GND connection of the cap.

    In your design, C85 is an example of a good implementation of this, where C49 is a bad example. Even C84 isn’t perfect helpful as there are 3 GND stitch vias depending on carrying the entire current needed locally by the FET. In my experience, 1uF is not enough to cover the full local current needed in 48V applications. Consider 10uF or more to round out the higher frequency current demand. With that said, the big electrolytic 620uF are good, they just need to put them closer to the FETs if you can. Doing the math, the DRV only needs 2-3A max, so 620uF is certainly a lot to be sitting next to VM.

    You’ll notice this is nebulous advice. I’m not giving equations or data. This is why engineers still talk about decoupling capacitors. Most notably, this is because it’s much easier to put footprints, test system in reality, and if the performance isn’t good enough, then we add in more caps, or change the existing cap values to higher values. Like the RC snubbers, this makes it experimental.

    HS DRAIN to LS SOURCE caps

    This has a very similar job to the decoupling because it provides charge to nodes or components that need the charge. One of the factors I forgot to mention in the previous section is that charge can only be provided from those caps if the reference is stable (e.g. GND is not bouncing) as the high impedance nature of the capacitors decreases as frequency increases, so current is rerouted through the cap, instead of to the component.

    In the case where the node between the LS source and sense resistor is also needs charge, we know the sense resistor has some impedance, both intended and parasitic, in its connection to GND. So, the bulk caps have to travel to through the sense resistor to provide charge to the node between the LS source an sense resistor. If GND is ringing and current is flowing through the sense resistor, charge has to fight against the flow.

    The HS drain to low side source cap prevents this because it is connected to VDRAIN, which is assumed to be stable, and can dump charge directly onto the node, instead of through the path of a sense resistor. If you’ve ever heard the concept of an AC GND, this is the same idea. VDRAIN becomes our AC GND instead of just GND.

    A lot of engineers underestimate the power of this fix. If GND or the sense resistor is ringing negative, or below GND, the HS Drain to LS source cap will provide charge in a low impedance and parasitic path. This is why waveforms are helpful for this. Keeping them around 1uF and as close to FET paths as possible, will help.

    Diodes

    I’m going to briefly acknowledge TVS diodes as I’m not an expert. Simply put, they’ll clamp a node to a voltage so no absolute maximum ratings are violated for the device. Current rating, clamping voltage, and response time are all at play here.

    A populate location is to connect the cathode to the GLx node, near the FET, and the anode to GND to help with negative transient spikes. From what I understand, these aren’t recommended as a replacement to the other methods as the simply reroute energy as opposed to suppress by filtering or decoupling.

    Layout techniques:

    Components can only take you so far, but layout is equally important. Here’s a bunch of quick wisdom.

    • The real PCBA has parasitic components that get added to the schematic, so to speak.
    • Long traces add capacitance and resistance.
    • Thin traces also add resistance and inductance.
    • 10mil/Amp is a rule of thumb for the minimum trace width but it also applies to vias (angular ring area).
    • Making traces thinner and smaller add impedance mismatch.
    • More current means higher voltage spiking. Component footprints add parasitics.
    • Vias in the path add parasitics.
    • The return path must be understand: DC current will spread out on the GND planes as far it can reach where high frequency current gravitate underneath the trace. This is why common GND is always better unless current will flow near the trace
    • Common ground is always better than split GND. Split GND is only ever used to divert large current or high frequency content away from sensitive components. That means the signal needs to be traveling towards those components to warrant a split GND.
    • Be the current, draw the loop from the source of the pin or component to the GND pin or external connector. Make it as small as possible. This means adding lots of vias or rearranging components
    • Order of importance or signals on an IC are voltage regulators (like VCP or VGLS), input regulators (like VM), signal path and higher current paths (like GHx and GLx), digital signals that switch often (like SPI), and digital signals that don’t switch often (like nFAULT) which means

    There’s plenty more in this app note: https://www.ti.com/lit/an/slva959a/slva959a.pdf

    Phew, that was a lot. Hope it helps.

     

    Best,

    -Cole

  • Hi Cole,

    Thanks for your extensive explanation. I did not know the concept of AC GND

    and HS drain to LS source caps, that may be really helpful in some cases.

    Alcor,

    I noticed that connector with motor phases contains also low power signals (probably Hall sensor signals).

    I would be careful about running high power and low power signals in the same cable. I do not say

    it is impossible, it can just bring some extra problems. Running them in separate shields. filters, transfer low power

    signals to higher voltage and/or current, differential pairs can be helpful.

    The PCB is 2oz copper thick, traces of VM bus and motor phases close to connector might be to thin for 50A current,

    unless they are copied to another layer/layers and stiched with lots of vias.

    Regards,

    Grzegorz

  • Thank you both for all these answers!