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DRV8353: Damaging DRV8353 above Vdrain = 50V

Part Number: DRV8353

I am using the DRV8353HRTAT to implement a 45 Hz trapezoidal drive waveform with a 4-MOSFET H-bridge to drive a specific load, so I'm only using 4 of the 6 outputs.  The trapezoid waveform is created by using 57kHz PWM to generate 2ms ramp up and ramp down intervals of the waveform, and the H-bridge is solid high/low or low/high during the non-ramp portions of the waveform.  The circuit works very well up to 50V, but above 50V I am damaging the DRV8353.  The MOSFETs seem unharmed.  Once damaged, I am seeing a near short to ground on SHA (roughly 40 ohms to ground).  Thinking it was the low-side MOSFET, I lifted the source pin on the FET and still saw the same near short.  That confirmed it was the IC and not the FET that was damaged.  Once the IC is damaged, it must be replaced to get the board working again.

I am using VM = 24V, and Vdrain I can set to 24V or vary between 43V and 85V.  When Vdrain gets above 50V is when I see damage occurring to the IC.

On one of the boards that I damaged, I actually heard and saw a tiny explosion on the DRV.  Visual examination showed a tiny crater on the IC near pin 5, which is VCP.  On this particular board, VCP is shorted to ground after this damage and I'm also seeing the typical near short to ground at the SHA pin.  I don't see damage at the SHB pin.  VCP has a 1uf 25V cap to Vdrain.  I checked this cap on another board and it measured 0.9uf, which is within tolerance.  I have another board working at Vdrain = 43V and VCP is sitting at about 53V, so that looks correct.

I'm running with 100 mA of gate drive selected, which seems to be enough to drive the FDD770N15A MOSFETs.

I am aware that the DRV8353 has many features to prevent damage in case of faults, but it is not protecting itself in my circuit, and I don't understand what is happening at higher voltages to cause the damage.  I am not getting close to the 100V spec on the IC.

I am afraid to damage more boards and was hoping that someone on this forum might have had a similar experience or can supply some insight.

  • Hi Brian,

    Can you share your schematic for us to review?

    We need to investigate further, but it may be that you are damaging the VCP ESD, meaning a high voltage was generated on SHx and overloaded the VCP regulator by back-driving it.

    Thanks,

    Matt

  • Never mind - we have the schematic through our mutual friend Cameron. We will review it.

  • I am hoping for a quick resolution, as the rest of the circuit is working perfectly and the client is very anxious to get working boards this week.  I hope to understand what modification must be done to keep the DRV IC safe.  This project is dead in the water for the moment until I get some feedback from you.  I don't see the point in blowing up more boards.

  • Absolutely Brian.

    Can you operate the system to the highest voltage that you are comfortable without causing damage and observe the voltage at SHA, GHA, VDRAIN, and VCP? (If phase A is not switching take a look at phase B instead)

    We will also reach out to set up a call.

    Unrelated to the issue at hand, but I wanted to point these out:

    • We recommend tying unused SPx/SNx to GND (Recommend tying SPB to the source of Q7 since it is the negative input for the overcurrent VDS monitor)

    Thanks,

    Matt

  • Hi Brian,

    I noticed that these MOSFETs have a large reverse recovery charge of 109nC, and are in D-PAK, meaning they have some significant lead inductance. This would lend to the possibility that SHA or SHB are spiking to a high voltage when switching. Mitigating this would require slowing down the rise/fall time (reducing IDRIVE, see below) or adding snubbers.

    In addition, the QGD is only 1.8nC (surprisingly small) and so a gate drive strength of 100mA may still be too high (fall time = QGD/IDRIVE = 18ns). You may need to add resistors in series with the gate to further slow down the rise and fall time, if you are already at the lowest setting. Alternatively, you can try to add external CGS (or tiny additional CGD) to stabilize the MOSFET.

    Thanks,

    Matt

  • I will make the scope shots and send to you ASAP.  Unfortunately, I am stuck with 4" of ground wire on my probes, don't have convenient ground TPs near the nets in question, and so will inevitably have some undershoot/overshoot that is due to just the non-ideal probing.

  • If I add resistance, any idea how we are talking about?  I know that adding too much resistance can cause excessive power dissipation in MOSFETs.  Also, we have 100 ns of deadtime that is fixed in this version of the DRV8353.  If we slow things down too much we could start to get partial shoot-through, yes?

  • Hi Brian,

    If you can solder a wire onto the bottom of R17, that may be close enough to GND for a reference.

    Based on my first order calculations, adding a resistor of 100-300 ohms looks like it can move the fall time from 18 ns up to around 34-67 ns. You're switching very fast already, so this shouldn't be a major contributor to the total MOSFET power dissipation.

    The driver has built-in shoot through protection which is not very easy to fool (monitors the gates to check if they are OFF or ON), as well as the 100ns dead time. Dead time is applied in a  "closed-loop" fashion, meaning the dead time starts when the driver sees the gate is OFF (<2V).

    Thanks,

    Matt

  • Actually, to me, the waveforms look pretty stinking great.  Attached are some scope shots: Ch1 = SHA, Ch2 = GHA, Ch3 = VDRAIN, Ch4 = VCP.  Idrive set to 100 mA.  Vdrain = 50V.  I have captured the 4 signals at various places during the PWM ramp up and ramp down intervals.  In the last set of shots, I turned off the zoom mode and tried to get maximum time resolution on my scope.  I don't see any issues.  Even the ground leads on my scope probes don't seem to impact things.

    I'm wondering if the turn-on sequence is important.  You will notice that I have a number of switches in my design.  Right now, I am 1) turning on the boost, 2) enabling the DRV, and finally, 3) enabling the SLG (this starts producing PWM waveforms, when disabled PWMs are both low).

    I have a zip file with scope shots.  How can I send them to this posting?

  • Click "Insert" and select "Image/Video/File"

  • These waveforms do look good, but I am still analyzing them. Is there any way to increase the resolution (samples per second), especially on a capture like 01012 & 01009? Alternatively, It would be good to zoom way in on one rising edge and one falling edge. At your current configuration, you are only getting 40ns per point (I think).

    Can you measure the failed unit to see the resistance between GHA (+) & SHA (-) as well as VCP (+) to GHA (-)?

    Thanks,

    Matt

  • Hi Brian,

    Another unrelated schematic review comment: VREF needs to be supplied with 3.3V or 5.0V for the current sense amplifier to work.

    Thanks,

    Matt

  • Matt, in response to your latest request:

    Board #009 measures 8.6 ohms between GHA and SHA (both polarities).  VCP to GHA is about 450k

    Board #007 measures 6.5 ohms between GHA and SHA (both polarities).  VCP to GHA is 69 ohms (both polarities).  This is the board with the crater at the VCP pin.

    More scope shots are attached.  With the time scale set to 20ns/div, I just kept hitting single trace and couldn't really control where in the PWM ramp I was looking at.  There is a combination of slow and fast edges.  One edge was on the order of 7ns.

    Program won't allow me to upload the zip file now, dang!

  • Hi,

    I would also check if LS Mosfet gates are kept low during switching on HS Mosfets.

    The problems starts with higher voltage so shoot through might be the problem.

    Regards,

    Grzegorz

  • That's a good catch!  What's strange is that I'm seeing a current waveform at SOA, but it actually swings below ground.  Probably, tying VREF to 3.3V would fix that.

  • So, with basically a short between GHA and SHA, the gate driver is getting smoked.  Agree?

  • Do you think shoot through could lead to the gate driver damage I am seeing?  Doesn't the DRV8353 prevent shoot through via deadtime, etc?  I suppose I could check GHA and GLA with my scope.

  • It's just a clue, I was thinking more about capacitive du/dt turning on of LS mosfets.

    Some interesting thing is that Vdrain is fluctuating only during PWM switching.

    It would mean that switching alone takes some power.

    Grzegorz

  • Well, based on our call this morning I did some more tests and damaged another IC.  I discovered that with Vdrain at about 55V, and with the circuit under load, the boost converter was tripping.  I placed a 2nd 0.01 ohm resistor on top of the current sense resistor to achieve an effective value of 5 milliohms.  After doing this, I turned on the circuit and slowly increased the Vdrain.  I heard a pop at Vdrain = 65V, the DRV was damaged, so I shut things down.  I was able to capture the signals requested by Matt: ch1 = nFAULT, ch2 = GHA, ch3 = SHA, ch4 = VCP.  I measured the following resistances on the damaged board: 

    SHA to GND = 1.8 ohms

    GHA to SHA = 1.2 ohms

    GLB to GND = 2.8 ohms

    GLA to GND = 145kohms

    GHB to GND = 105kohms

    VCP to GND = 0.9 ohms

    no visible crater this time, although I heard a definite pop.

    The scope shot is attached.  It was triggered on nFAULT, but the nFAULT signal looks pretty crazy, going much higher in voltage than usual.

  • What's the next step?  Should I beef up the SHA trace with a wire and put 100 ohm resistors in series with the 4 gate inputs?

  • Yes. Even with no load attached I can see current activity in the SOA output during the PWM interval, but none in the non-ramp intervals.  Of course, the current increases quite a bit with the load attached.

  • adding more traces at different zoom levels. D3.zip

  • It looks like things went south at the end of a narrow negative pulse that occurred towards the end of the PWM ramp interval.  This is when the current in the H-bridge is the highest as the load capacitor is reversing polarity.  The pulse gets about 50% back up and then, POOF.  nFAULT goes low about 4us later.

  • If the load is capacitive type and is connected between two half bridges, maybe it would be worth

    to check what is happening on second half bridge (SHB, SPB, GLB and GHB) for any

    spikes during switching the A side.

  • Hello Brian,

    First impressions look like the damage might have actually occurred on the rising edge of the new PWM pulse. I'm going to give a play by play:

    • So the gate and phase drop down with the falling edge of the PWM and we see that negative spike.
      • It doesn't look particularly bigger than the rest of the ones that come before (unless the resolution didn't pick it up), so I'm not sure it was damaged there.
    • Then, we have the dead time,
      • Which does look like it gets smaller in comparison to the other PWMs. The previous one looks just as long so I don't think there's problems there or first glance but I'll let it open to the possibility that it was damaged here
    • Only during that rising gate edge do we see the spike on VCP and VCP starts to descend.
    • Looks like the second hump of the rising edge lines up with nFAULT glitching a bit, so we're probably seeing the fallout of the damage here.
    • The nFAULT goes low around 4us after rising edge, which is what we expect from on the GDF (which should trigger) and OCP deglitch.
    • Fault releases later.
      • Note, that CBC or cycle by cycle operation means the device will be cleared by another input PWM (which, correct me if I'm wrong) will not stop after nFAULT flips, and the PWMs will continue to go. So this behavior probably "expected"
    • Crazy stuff happens after this and it looks like the rails are all collapsed by then so we don't have much of a clue what's happening there.

    Still boils down to "Why does VCP start to pull so much current that it starts to dip?". The shorts agree with this speculation but still, I can't answer why the shorts happen in the first place!

    So, now what? Well, I think we start trying to correct the things that look suspicious, like you said, the SHA thickness and adding gate resistors, at see if we can prevent the damage.

    Best,

    -Cole

  • The load is not strictly capacitive, as there are 100uH inductors on each side before getting to any capacitors.  The voltage at the load is a smooth ramped trapezoidal.  Of course, the current flow in the inductors will generate back EMF when the H-bridge changes state.  When the MOSFETs are on this current will be conducted to VDRAIN or GND appropriately. During the deadtime interval, the current will be conducted to VDRAIN or GND by the body diodes of the MOSFETs.

    The PSPICE simulation below shows SHA and the voltage on the glass (after filtering).

  • Got to leave now and drive my wife to her COVID shot.  I try a fresh board tomorrow and add the wire to beef up the SHA connection the DRV and add 200 ohm resistors in all 4 gate signals.

  • Good news!  I took an undamaged board and added 200 ohm resistors in series with each gate.  I also added a wire on SHA in parallel with the whimpy trace on the bottom of the board. I have taken the board up to 80V unloaded with no issues.  I have taken the board up to 65V under full load with no issues.  At Vdrain = 70V, my boost converter is tripping on overcurrent, so I need to adjust the sense resistor.  But, no damage so far.  Rise and fall times on SHA and SHB are slower and look pretty nice. 

  • Here are the waveforms for loaded at Vdrain = 65V.  Ch1 = 45 Hz, Ch2 = SHA, Ch3 = SHB, Ch4 = SOA.

  • Hi Brian,

    That's very good to hear! Keep us posted if you run into any other issues.

    Cole & I were talking on our side and definitely want to recommend switching your control mode to PWM'ing only one side of the H-bridge at a time. This would prevent any unwanted "charge pump" effect due to your capacitive load, especially when there is very little current flowing through the inductors.

    To do this, you would need to:

    • Use 1x PWM mode of the device by disconnecting R13 (MODE = Hi-Z)
    • Use INHC as a the  "direction flipping" pin
    • Tie PWM to INHA (you would not need an inverted PWM as it is generated internally in this mode)
    • Tie INLC to DVDD (needs to be logic high to turn off the BRAKE)
    • Tie INLA, INLB to GND, Tie INHB to DVDD (these are the state control inputs)

    This allows you to operate in state 3: A-->B when INHC = H and state 6: B-->A when INHC = L. (From table 3 in the datasheet).

    Thanks,

    Matt

  • Matt & Cole, thanks again for your input and help.  I am not able to visualize the control signals or what SHA and SHB should look like in the scheme you propose.  Can you sketch up something quick and dirty?  Once I understand what you are proposing I can modify my PSPICE sim to see what the circuit does.

  • Hi Brian,

    Take a look at my image below:

    Thanks,

    Matt