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DRV8912-Q1: DRV8912 SPI timing tSC_SPI - what is it?

Mitch Berkson
Prodigy 30 points
Part Number: DRV8912-Q1

In the DRV8912-Q1 Timing Requirements, there is a spec for "Successive SPI write gaps" and it is nominally 2.5us. What is that referring to?

  • 0
    TI__Guru 54665 points

    Mitch,

    My understanding is this is the time to pause between successive writes to the device.  

    Does this cause you some problems in your system?

    Regards,

    Ryan

  • 0 in reply to Ryan Kehr
    Prodigy 30 points

    That is what is unclear to me. It would make sense that the minimum SCS high time of 600ns would be the parameter which ensures a minimum time between either reads or writes. Is the write gap an additional requirement?

    The name "write gap" is confusing and raises additional questions: If there is a minimum time between successive writes, why is this parameter only given as a nominal value instead of a minimum? What is the write gap referring to - a minimum time between SCS going low on successive writes? Or something else?

    It is a concern for me because I am doing multiple writes to multiple daisy-chained devices.

  • 0 in reply to Mitch Berkson
    TI__Guru 54665 points

    Mitch,

    I am digging into this.  I am not seeing this specification in any of our other motor driver datasheets, so I am trying to understand the reasoning here on this device.  Please give me some more time.  

    Regards,

    Ryan

  • 0 in reply to Mitch Berkson
    TI__Guru 56650 points

    Mitch,

    I got feedback from design.

    During the SPI write/read gap, the nSCS should be high. 

    The SPI write/read gap timing is related to the IC internal clock. The minimum tsc-spi is about two clock cycles which is about 1.6us minimum.

    Please ignore the 600ns thi_nscs.

    Regards,

    Wang Li

  • 0 in reply to Wang5577
    Prodigy 30 points

    Thanks for following up. That makes sense with what I see.