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DRV3245E-Q1: nFault not clearing and IC becoming very very warm

Part Number: DRV3245E-Q1
Other Parts Discussed in Thread: DRV8323

I have layed out a new PCA revision of a motor control circuit, replacing the TI DRV8323 with a TI DRV3245A motor driver.  There were obvious pin layout changes that were noted and implemented.

I have noted two issues (with 3 separate driver circuits):

  1. The nFault pin remains LOW (0) after initialization.  The fault registers and the fault bit do not report any faults.
    1. Initialization order:
      1. Drive DRV_OFF trace HIGH (1), to turn the pre-drivers OFF
      2. Drive Enable pin HIGH.
      3. Wait 50 ms
      4. Write to the SPI registers
  2. Once we have initialized the driver IC , as stated above, and the DRV_OFF is changed from OFF (1) to ON (0), the DRV3245A chip becomes very very warm in less than 5 seconds

Schematic of DRV3245A layout

Upon a physical inspection, there does not seem to be a layout issue, using the correct passive values as recommended per the data sheet.

PWM is 0

Brake is 1

Direction is 1

Please advise.

Rick Thompson

  • Rick,

    I need to review your schematic and check something with the team, I will get back to you by EoD tomorrow.

    Regards,

    -Adam

  • Hi Rick,

    Have you tried grounding the unused SHx and SPx pins? We have seen that these pins may float when not connected and cause a fault trip.

    Thanks,

    Matt

  • Hi Matt,

    Had you meant to say SN instead of SH?  SH is connected to the HS and LS FETs.  SN and SP are presently floating.  To answer your question, no I have not tried to ground the unused pins.  It it your recommendation to ground them?

    **An important update**

    I found that the charge pump pins were incorrectly connected.  Looking at the schematic I provided,  they are paired CP1H and CP2H and CP1L and CP2L!  The correct pairing is CP1H and CP1L and CP2H and CP2L.  I was able to make modifications to correct the pinout.   My problem now is that I am getting an Overtemperature warning (IC Status 0 Register, Bit 0).  The component is not hot, so I'm not sure why the warning.  The FAULT field does not indicate a fault (IC Status 0 Register, Bit 10).  The nFault output is LOW, indicating a fault.  This is a contradiction!  I am unable to clear the fault.  Would you speak to this condition?  Could this be related to how the DRV3245A is initialized?  What is the initialization procedure for preparing the driver to control a motor?

  • Yes! I meant SNx. Glad you could read what I was intending to say rather than what I actually said.

    We do recommend to ground unused CSA inputs (the outputs are OK to float)

    Thanks,

    Matt

  • Thanks for the quick reply.  Are you able to address the fault condition reporting and the initialization procedure for the DRV3245 driver?

  • Richard,

    If you completely power cycle the board (including MCU) and restart, does the fault persist? Can you clear the fault using the SPI CLR_FLTs command? The CLR_FLTS command is on bit D1, address 0x9.

    Maybe the original device got damaged? Have you tried more than one IC after correcting the CPH/CPL configuration?

    Regards,

    -Adam

  • Adam,

    Yes I restarted the board and the fault continues.  The fault that is reported is the Overtemperature warning (IC Status 0 Register, bit1: 1). The nFault pin is HIGH (3.3V), suggesting that the fault is clear.    I checked the nFault pin and it indicates that there is no fault; it is HIGH (3.3V).  I cleared the CLR_FLTS bit (IC Operation  Register bit1: 0).  The Overtemperature warning bit continues to be HIGH.

    It is possible that the DRV3245 is damaged.  

    What is the initialization procedure for the DRV3245 driver?

    Rick T

  • Rick,

    The init procedure is outlined in the datasheet and is not likely to have caused damage but I think unfortunately the chip may have been damaged, could you try a second IC please?

    Regards,

    -Adam

  • Adam,

    I incorrectly reported that there was an Overtemperature Warning (IC Status 0 Register, bit1).  There was not a warning.  I interpreted the hex value incorrectly.

    I tried a PCA that had not been energized, with corrected Charge Pump capacitor layout.  I was unable to drive a motor.  We too believe the initialization process is correct.  There are no faults reported in the fault registers, nFault is HIGH and DRV_OFF is LOW. The PWM (duty Cycle) is 100% and the Brake is HIGH.  All verified by reading their respective pins.

    A problem exists that I cannot answer.  There is 10V across the motor coils, whether DRV_OFF is HIGH or LOW.  Do you know why that may be?  There is no PWM signal.  It is not affected by whether the Brake is HIGH or LOW.  It is not affected by motor rotor position.  The driver is reading the Hall input signals.  There is a 18mA increase in current.  The 10V across the motor coils goes to 0V when the driver Enable pin goes LOW, as expected.  There are no Fault codes reported.

    I have a layout question.  We are using one (1) LS current sense resistor.  How does that affect the layout of SLx?  Presently the three SL inputs are brought back from the source pin of each LS FET to there respective inputs.  See the attached schematic layout.

    Regards,

    Rick T

  • Rick,

    Good to hear that the motor is now spinning!

    Due to the design of our output stage, when the charge pump is active there is a small amount of leakage through the high side pull-up FET internal to the device. The SHX nodes are shorted to their respective GHX node since the high side FETs are OFF and therefore the VGS is shorted to prevent turn-on. If you disable the charge pump or turn on the low side FETs you will see that this voltage goes away.

    The schematic and layout for SL looks correct, we want the SL connection shared if only one of the CSA is used.

    Regards,

    -Adam

  • Adam,  Sorry about the empty replies.  The return command sent the reply.  To correct an earlier statement by you, I did not get a motor running.  I have a new question.  Not being able to drive a motor, I tried to control the LS and HS FETs in 6-PWM mode.  I configured the Gate Drive Control Register (0x07), bit 8-7 to 00b.  INLA and INLA were brought HIGH (3.3V).  INHB and INLB were brought HIGH (3.3V) and INHC and INLC were brought LOW (0V).  My understanding, according to Table 1. 6-PWM Truth Table, was that when the 3 predriver sections were enabled (DRV_OFF --> 0V), all the gate signals (GHA, GLA, GHB, GLB, GHC and GLC) would all be LOW; FETs OFF.  I turned on the predrivers and the HS gates went HIGH, turning ON the HS FETs.  I was unable to determine the state of the LS FETs at that time.  Was I incorrect in my understanding of Table 1 or is there another explanation?  Regards, Rick.

  • Hi Adam,

    I would like to setup a meeting with your TI FAE who is an expert with the DRV3245A driver.  I need to jump start the troubleshooting process that we are in here at Toro.  Would you provide me the contact information so I can setup a meeting.

    Regards,

    Rick T

  • Hi Rick,

    Adam is out of office until Thursday but I will connect you with the rest of the team directly. Please accept my friendship request through the E2E system.

    Thanks,

    Matt

  • Issue resolved by modifying the initialization sequence of ENABLE_DRV