DRV8301: Ringing on high side Vgs at turn on (may be casuing Vds over current)

Part Number: DRV8301
Other Parts Discussed in Thread: DRV8353

I have a condition where the phase current appears deformed or limited due to the over current fault from the Vds measurement by the DRV8301.  I increased the Vds threshold incrementally to the maximum and the condition was still present.  When the OC mode is disabled completely the condition was no longer present which allowed me to investigate further.   I was able to observe an odd condition at the high side Vgs and at the resulting Vds.  At essentially the same point in the phase current cycle I recorded high frequency ringing on the HS Vgs at turn on.  I should note that it is visible on all three phases at the same time in the phase cycle for each phase, the images below are for phase C.  I believe the ringing results in the FET not fully biased on which causes the Vds OC trip level to be exceeded.  I have the gate current set to 250mA (DRV8301_PeakCurrent_0p25_A).   The images below show the condition with each image further zoomed in (Vds OC is turned off).  It doesn't seem to be a function of bus voltage or motor parameters, mainly phase current level.  The high side measurements are made with differential probes and the FETs are TK100E06N1.

  • Do you know what may be causing this high frequency ringing on Vgs? 
  • Are there other measurements you would like to see to help?

  • Hi Mike,

    Can you share all of your DRV8301 register settings and schematic file?

    Thanks,

    Matt

  • Hi,

    If Vgs voltage is measured correctly (13V and 15V) it is out specs.

    According to datasheet page 8 it should be 11.5V max.

    Regards,

    Grzegorz

  • Hi Mike,

    I synced up with Matt on the additional details you provided to him on private message. After looking at the data  with Matt there are a few things to note:

    1. Based on your Vds (LS) waveforms, it looks like the supply voltage is 48V. When looking at your schematic I noticed that the voltage rating of your capacitors were between 25V and 50V. In general, it is best practice to have the voltage rating of the capacitor to be 2x the voltage that will be seen on a particular pin. This is due to capacitor derating. The CPH-CPL capacitor in your schematic is rated for 25V, but that capacitor should be rated for VM voltage so I would recommend using a 100V capacitor. Additionally, for all capacitors attached to the 48V supply voltage, I would recommend using 100V rated capacitors. 

    2. Make sure that the CP1-CP2 capacitor, bootstrap capacitors, GVDD capacitor, and PVDD bypass capacitor are as close as possible to the device in the layout.

    3. If you still see the issues persist after replacing the necessary capacitors with the appropriate voltage rated capacitors, would you be able to supply a plot showing the GVDD voltage as well as the Vgs (HS) voltage  to see if there is a rise in the GVDD voltage that corresponds to the rise in the Vgs (HS) voltage? 

    4. What is the package size for the zener diodes on the gate? it is possible that this could be introducing undesired capacitance. 

    Regards,

    Anthony 

  • Hi Anthony,

    Thank you for the feedback.  Below are responses in red to your comments.  Also, I'm not sure if you saw my comments to Matt via private message yesterday, but I found if I increase the gate current from 250mA to 700mA, the ringing was eliminated and I can operate with the Vds OC enabled without issue.  I think the initial issue is resoved but I would like to understand why additional gate current stop the ringing.

    1. Based on your Vds (LS) waveforms, it looks like the supply voltage is 48V. When looking at your schematic I noticed that the voltage rating of your capacitors were between 25V and 50V. In general, it is best practice to have the voltage rating of the capacitor to be 2x the voltage that will be seen on a particular pin. This is due to capacitor derating. The CPH-CPL capacitor in your schematic is rated for 25V, but that capacitor should be rated for VM voltage so I would recommend using a 100V capacitor. Additionally, for all capacitors attached to the 48V supply voltage, I would recommend using 100V rated capacitors. 

    The schematic I sent is for the production execution has the bus voltage is supplied from a 12V lead acid battery, where the nominal voltage is ~14V.  I am utilizing this module to test a different motor in another application with a bus voltage of 50 volts.  I did replace many of the capacitors to support the higher bus voltage so I don't think and of the ratings are being exceeded.  I agree with the 2X voltage rating for capacitors and certainly will have those parts in the production module.  Sorry for the confusion. 

    I assume CPH-CPL is CP1-CP2, C22 on the schematic I sent to you.  Yes, this capacitor was changed for a 50V because it's what I had in the lab.  I will have a 100V in there when it comes in. Do you think a 50V rating will cause an issue for a bench test.

    2. Make sure that the CP1-CP2 capacitor, bootstrap capacitors, GVDD capacitor, and PVDD bypass capacitor are as close as possible to the device in the layout.

    Here is the layout showing the components you referenced.  I think it is a pretty decent loyout, but not perfect.  The GVDD capacitor has a dedicated trace back to the DRV8301 slug on the lext layer down from the layer shown.  I welcome any comments.

    3. If you still see the issues persist after replacing the necessary capacitors with the appropriate voltage rated capacitors, would you be able to supply a plot showing the GVDD voltage as well as the Vgs (HS) voltage  to see if there is a rise in the GVDD voltage that corresponds to the rise in the Vgs (HS) voltage? 

    I see the rise in Vgs (HS) but do not see the rise on GVDD.  The level of the gate voltage in this part of the cycle increases as the corresponding phase current magnitude increases.  I measured 14.5 volts for Vgs (HS).  I have a 2.2µF, 50V capacitor across GVDD to PGND and the average voltage is ≈10.9 volts.

        

    4. What is the package size for the zener diodes on the gate? it is possible that this could be introducing undesired capacitance.

    The package is a SOT23.

  • Hi Mike, 

    Thanks for the additional info! Yes, Matt did share with me the extra waveforms. I will take a look at this in more detail over the next couple days and try to get back to you on Friday.

    Regards,

    Anthony 

  • Hi All,

    I have some theory regarding increased Vgs voltage.

    I just guess (please, correct me if I am wrong) when Vgs is rising above 10V current direction is from half-bridge to motor (half of sine wave).

    I can see (third diagram from the top) some small step in Vds (HS and LS) just before turning on the Vgs (HS) caused probably by

    turning off the LS Mosfet and PWM duty cycle is higher than 50%, so I guess current goes to motor from that phase.

    If current goes in this direction then reverse recovery of LS mosfet body diode occurs and usually it is causing

    negative spikes on switching node of half-bridge, we can see around -5V spikes on Vds (LS) on inductance of Mosfet and

    probably that is not all (probably there are also other parasitic inductances from LS Mosfet source to GND).

    Negative spikes on switching node could pump bootstrap cap to higher voltage (V_GVDD + voltage of spikes).

    It would be interesting to see voltage between SW node and ground plane, I suspect voltage spikes can be higher than -5V.

    I do not have any explanation why ringing occurs on Vgs for so long and disappear with higher Idrive current.

    Maybe it would be worth to check voltages on INH_X and INL_X when that ringing occurs.

    Regards,

    Grzegorz

  • It appears the ringing or oscillation condition on Vgs (HS) is causing the gate voltage magnitude to increase.  In the first image multiple ringing conditions are shown and the corresponding increase in bootstrap/gate voltage.  The next three images show the signals requested Grzegorz above. There is negative voltage present during the ringing at the switch node to Grzegorz's point.

          

    As I mentioned previously the excessive ringing was eliminated when I increased the peak gate current from 250mA to 700mA.  However, there is still an increase (smaller) in the gate voltage.  I increased the peak gate current to the maximum (1.7A) to see if the it had an effect on the bootstrap cap/gate voltage and it appeared to not make a difference (≈14.2 volts maximum) compared to the 700mA value.  See comparison below.

    My plan was to test with a DRV8353 due to the increased voltage rating (55V nominal buss voltage), but I (we) have not been able to get the EVM board to connect and function.  I am working with other TI folks to get this working, but it is taking quite while.

  • Hi Mike,

    Thanks for all information that you provided.

    I think there is a good chance that reducing negative spikes on SW node will

    limit voltage rise on bootstrap caps.

    I thought that Vgs ringing might be caused originally by ground bounce and

    INH_C to GND voltage fluctuations but apparently it is not the case.

    Regards,

    Grzegorz

  • Hi Mike,

    I plan on discussing these waveforms with one of my coworkers tomorrow. Could you provide a waveform showing the bus voltage? I want to see if the ringing also appears on VBUS.

    Regards,

    Anthony

  • Hi,

    A few more thoughts.

    Looking on the second waveforms from last Mike's post I can see negative spikes on SW node

    while turning on HS mosfet (caused probably by reverse recovery of LS mosfet body diode) and

    while turning off HS mosfet (caused probably by negative di/dt during turning off HS mosfet).

    Both spikes occurs because of parasitic inductances of mosfet (leaded package equal high parasitic inductances),

    inductance of sense resistor (if it is present) and inductances of pcb traces.

    If circuit is with two sense resistors like on page 14 of datasheet the influence of sense resistor's inductance

    on voltage spikes can be evaluated by comparing SW spikes between half-bridge with sense resistor and the one without it.

    Parasitic inductance of sense resistors might be bypassed with a small high speed schottky diode (it has to withstand

    current only for a very short time during voltage spike) or maybe small MLCC cap (I have not verified

    a method with a cap yet).

    To reduce these SW negative spikes I would also consider changing mosfet for a one with leadless package and/or using

    RC snubbers and/or improving pcb layout.

    Voltage spikes of -20V value are quite capable of killing driver chip, it is a very good thing that driver works at all.

    Coming back to Vgs ringing I would try to look for a cause in gate circuit and pcb layout.

    It could be useful to compare Vgs voltage on mosfet to voltage between GH_X and SH_X pins as close

    to DRV8301 as possible when that ringing occurs.

    I would also check Vgs waveform of LS mosfet if there are no any problems - just in case.

    Regards,

    Grzegorz

  • Hi Mike,

    I agree with a lot of what Grzegorz mentioned in his recent post: the negative transients on the SHx-PGND measurement are likely causing the bootstrap capacitor to overcharge and that is why you see the increase in VGS voltage during high negative currents through the phase. one way to confirm this would be to differentially measure the voltage across the bootstrap capacitor. These negative transients are large (over -10V), and as Grezgorz mentioned this is operating out side the ratings of the device. I think that taking a thorough look at the layout and adding a few extra components (as discussed below) will go along way to improving your design. 

    The ringing that you see on the high side source could have a few possible causes: as Grzegorz mentioned high inductance paths will cause ringing and the sense resistor packages that you are using are likely adding considerable amounts of inductance to the ground path. This could be reduced by applying a capacitor from the drain of the high side FET to the top of the sense resistor. I would recommend starting with a 10uF cap. Additionally RC snubbers may help reduce some of the issues here. You can check out this article on RC snubbers here as well as Matt Hein's article on board parasitics here

    If you would like to private message me with your PCB schematic files I can review them and provide feedback on considerations to improve the layout. A good article addressing PCB layout design considerations can be found here

    Regarding the increase in the peak current reducing the ringing on the gate: This is surprising to see since usually increasing the switching speed of your FETs by increasing the gate current results in more ringing. One possible reason you are seeing a reduction of oscillation for higher gate currents could be that the Cgs of the FET and the inductance of the gates are causing ringing at the resonant frequency, and increasing the gate current results in a shorter duration in the resonant frequency range. One way to test this would be to add a small capacitor from the gate to source of the FET to see if this reduces the ringing.

    Regards,

    Anthony 

  • Hi All,

    I agree with all that Anthony said.

    Looking at PCB layout at the beginning of that post I have just a few more thoughts. I assume that 6 large footprints around driver chip are mosfets.

    Probably most of TI motor drivers have most of their high power pins assigned to one side of the chip and most of low signal pins assigned to other side. It allows to separate high current and high di/dt circuits from others.

    Looking at pcb picture I can see that LS Mosfets are placed on high power side of DRV8301 but HS Mosfets are placed on low power signal side of the chip. That probably means there are long traces between LS mosfets drains and HS mosfets sources that go under or close to DRV8301 and other low power signals. These high current and high di/dt traces may cause some extra problems like:

    - increased parasitic inductance in high di/dt loop (increased ringing and EMI)

    - increased magnetic coupling to more sensitive circuits (increased interference in these circuits).

    Coming back to Vgs ringing on HS mosfets. Frequency of that ringing is around 4.2 MHz, Cgs of mosfet is around 10nF so inductance should be around 140nH, what is a lot. If that ringing is caused by LC resonance I would try to decrease Q of that RLC circuit. One way to try out would be increasing R by gate resistors. I do not know if they are present for HS mosfets, I can not see them in case of LS mosfets. Circuit on page 25 of datasheet shows 10 Ohm gate resistors, TK100E06N1 is a big transistor, maybe 4.7 or 2.2 Ohm would be better. Another way would be decreasing parasitic inductance of gate trace and its return. Gate trace should be possible short and wide and I think well referenced to return path, in that case I think return path would be trace that goes from HS mosfet source to LS mosfet drain and then to SH_X pin of DRV8301. Caution should be taken when changing pcb layers by trace with vias.

    Any changes that I proposed can make things better or worse ie. blow DRV8301 or mosfets.

    I think the pcb layout is not optimal but the circuit works and maybe some small changes can make it work properly.

    Regards,

    Grzegorz

  • Hi Grzegorz,

    Thanks for your input!

    Mike,

    I think optimizing your layout and adding some RC snubbers/ bypass capacitors as was discussed will go a long way in helping mitigate the issues you are experiencing. Adding small gate resistors as Grzegorz mentioned will allow you to have more control on your gate current. If you want some feedback on your layout then feel free to private message me with the PCB files and I will take a look at them.

    Regards,

    Anthony 

  • Anthony and Grzegorz,

    Thank you for the feedback.  I will pursue some of the ideas in the comments.

    Anthony, I will send you the layout and schematic files, but the messaging feature of E2E will not allow me to message you.

    Thanks,

    Mike

  • Hi Mike,

    Sounds good, I will PM you my email.

    Regards,

    Anthony 

  • Based on the feedback I was able to conduct the following tests with the results in blue.  The g-s/bootstrap cap still has an increase in voltage over each cycle.  I will be adding additional local bus capacitance once I receive the 100 volt parts.

    1. Add small capacitor g-s to see if ringing is reduced due to resonant shifting.  Resonance is due to L in "large" gate leads and Cgs  I added 100pF across g-s HS and the Vgs (HS) ringing went away (see below in red on image)
    2. Direct connections to LS drain from bootstrap cap(-). I made these jumpers (shown in red below) and the ringing is no longer there.
    3. Add a large cap 10µF from HS drain to the top of the sense resistor.  I was able to add ~2µF across the shunt resistor top and the drain for each phase.  This also eliminated the Vgs ringing. I will add additional capacitance once the parts arrive.
    4. Differential measurement across bootstrap capacitor  Voltage  mirrors g-s voltage magnitude.
    5. In all cases above, the Vgs (HS) was eliminated but the bootstrap cap voltage still increases (not as high in magnitude though).  Each test was done independently from the other.

  • Hi Mike, 

    Thanks for the additional info! I am glad to see that adding some additional capacitance helped mitigate some of the issues. I believe that negative transients on the high side source node are causing the increase in the bootstrap capacitor voltage and thus the HS VGS voltage. I will review your layout over the next couple days to see if there are ways we can minimize negative transients at the phase node.  

    Regards,

    Anthony