https://e2e.ti.com/support/motor-drivers-group/motor-drivers/Products covered in this section are TI's DRV family of motor drivers. Learn more at www.ti.com/motorcontrol.en-USTelligent Community 13https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692402/mcf8329a-mcf8329a-new-device-eeprom-contents-vs-evm-and-production-programmingSat, 24 Oct 2026 06:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3838de5e-d135-49ad-a09a-a69ea1e7849eKavana L BPart Number: MCF8329A Other Parts Discussed in Thread: MCF8329EVM Hello, We are designing a custom board with the MCF8329A. Our motor runs well on the MCF8329EVM using the register values already in the device; we have not changed anything in Motor Studio. On our board we only use the SPEED pin (analog mode, fast/slow/park levels) and do not want to fit a USB-to-I2C interface. 1. Does a new MCF8329A ic have the same EEPROM contents as the device on the EVM, or is the EVM device pre-programmed? 2. If new devices need programming, can the MCF8329EVM be used to program our board through SDA/SCL test pads? If not, what do you recommend for production? 3. After programming, how should SDA and SCL be connected if I2C is not used? 4. How should we set MAX_SPEED and the motor parameters (resistance, inductance, BEMF constant) for our motor? Can the device measure these automatically (MPET) and use them without I2C, or must they always be written to EEPROM over I2C? Thank you.MCF8329AMCF8329EVMTest & Measurementhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691647/mcf8329a-evaluation-board-altium-library-access/6520272Sat, 24 Oct 2026 02:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6cb3048c-42bc-4e49-bb6c-9d0790f800b3DhineshHi Michael, Please find the footprint and schematic symbol library attached. e2e.ti.com/.../MD067E.zip Thanks, Dhineshhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692133/drv8906-q1-protection-function-malfunctoin-possibility-on-specific-configuration/6520190Fri, 23 Oct 2026 21:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9c5cba03-7268-4bca-af68-11415a7bab07Joshua Horlander CruzHi Ochi, I dont think I fully understand the question, but I think the question is why an OLD report won't be reported for the shown configuration? If this is the question, then OLD would not be expected only so long as OUT2 is not enabled when OUT3 or OUT1 are not enabled since if it were then OLD would be reported. Although the DRV8906-Q1 has the option to disable OLD for specific outputs so you could disable OLD for OUT2 and leave OLD on for OUT1 and OUT3 so open load conditions can still be detected. With OUT2 not having OLD on, OUT2 can be left on all the time and not cause an OLD report. Regards, Joshuahttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691924/drv3946-q1-drv3946-peak-and-hold-current-regulation-not-reaching-configured-values/6520085Fri, 23 Oct 2026 18:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:eddce597-cc88-4712-8aad-eca4965ee49aDavid MedisHi Debarpan, To configure internal current regulation peak and hold currents the Channel Control should be set to Internal Current Regulation, set CHx_PC and CHx_HC, and set channel peak time duration CHx_PT. What is the set peak time duration? What is the R, L of load? Best, Davidhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691932/drv8220-request-for-alternate-part-for-obsolete-h-bridge-driver-si9986cy-t1-e3/6519953Fri, 23 Oct 2026 16:14:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bab89287-bd18-4bf5-a020-d0a47e6943feYuzhou YaoHi Santhosh, Thank you for providing details. Unfortunately, we don't have a device that has exact same package, pin-to-pin compatibility, and identical truth table/functionality as SI9986CY-T1-E3 The closest alternative would be DRV8210DRLR, which is a is a DRL package, not an SOIC-8 as SI9986CY-T1-E3. DRV8210 doesn't have S_A and S_B pins. But it still allows putting a small shunt resistor on the GND pin that can provide current sense information. Please refer to the datasheet 9.2.4 section. The truth table of DRV8210DRLR is attached below. The Hi-Z mode and brake mode is reversed compared to SI9986CY-T1-E3. Otherwise these two devices have same functionality. If you decide to go with DRV8210DRLR, we will be happy to review the schematic and PCB layout for you. Please let us know if you have any further questions. Thank you. Best, Yuzhouhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691647/mcf8329a-evaluation-board-altium-library-access/6519775Fri, 23 Oct 2026 13:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:95fa6d20-39a9-4915-b4bb-c882ccbf2b3aMichael ZarlingThank you Dhinesh. Can you also please generate a schematic symbol library from the complete schematic?https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691712/drv3901-q1-afe-not-answering-the-call-mail/6519756Fri, 23 Oct 2026 13:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5868ef2a-3e0c-40a3-a458-7856831de71fIbinu Alaudeen NadeeraHi Shyam, I have reached out to field team and i expect a call from them soon. If you do not hear back please let me know. Thanks, Ibinuhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692070/mcf8316d-low-inductance-motor/6519503Fri, 23 Oct 2026 08:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5298d3b0-5c05-4ac1-bee1-2f4ebbf9d9bbuser5163865Hi Venkatadri S-san, Thank you for your support. I will check the application with my customer and then return here. Best regards, Hiroshihttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691924/drv3946-q1-drv3946-peak-and-hold-current-regulation-not-reaching-configured-values/6519459Fri, 23 Oct 2026 07:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7f96fb6b-a652-4e1d-93ed-17c9594e2b59Debarpan BoseHello David, Can you please give an example with all the necessary configurations that should be set to achieve the internal current regulation as per desired peak and hold current parameters? Thanks, Debarpanhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692133/drv8906-q1-protection-function-malfunctoin-possibility-on-specific-configurationFri, 23 Oct 2026 06:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b66df74a-a118-4515-8410-6d250bcaec22Yoshiki OchiPart Number: DRV8906-Q1 Hi team, DRV8906-Q1 is used as following conditoin, OUT1 - OUT3 is used to drive 2-motors. Could we say no malfunction protection triggered during following motor configuration especially for open load detection? Why? Regards, OchiDRV8906-Q1https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692070/mcf8316d-low-inductance-motor/6519349Fri, 23 Oct 2026 06:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c4c57ba5-520f-47cf-bb08-717f8302acb3Venkatadri Shantaram84961Hi Hiroshi-san, The MCF8316D (8A peak), MCF8315D (4A peak), and MCT8315Z are all viable options. Since the motor utilizes Hall sensors, the MCT8315Z would be the best fit, provided the customer does not require sinusoidal control or specific acoustic performance. I also recommend exploring the MCF8315D for its SmartTune feature; this would provide an easier migration path should the customer decide to move to sensorless control in the future. Could you please clarify what the end application is? Thanks and best regards, Venkatadri Shttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692083/lmr14050qdprevm-about-the-soft-start-capacitor-selection---css/6519332Fri, 23 Oct 2026 05:55:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:172ebe4e-f737-40ed-bfd8-30ab2c25af1dSourish NandyHello Peng, Kindly check out the following e2e thread and see if it resolves your doubt: (+) LMR14020-Q1: WSON package soft start maximum Css value - Power management forum - Power management - TI E2E support forums Regards, Sourishhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691803/am2432-new-patch-version-6-5-103-of-pru-am2432-cannot-connect-with-inovance-h5u-plc-through-ethercat/6519305Fri, 23 Oct 2026 05:31:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9e218efb-0bc4-4fc1-a518-8f4f54b20838Aaron ThomasHi currinwang Firstly, may I know which EtherCAT demo are you using - EtherCAT Beckhoff SSC Demo or TI Stack Demo ? If Beckhoff SSC Demo is used, have you included the changes from tiescbsp.c and tiescbsp.h files in addition to the firmware headers? [quote userid="568853" url="~/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691803/am2432-new-patch-version-6-5-103-of-pru-am2432-cannot-connect-with-inovance-h5u-plc-through-ethercat"] However, it can be properly connected to the Omron controller and TwinCAT. [/quote] By connected, do you mean scan is failing or the scan is successful and the state transition to OP is failing? If the latter is the case, can you check the values in the following registers: Physical Address: 0x30090ED0, 0x30090ED2, 0x30090ED3. 0x300B2010 to 0x300B2013 : MII_RT_TXCFG0 Register 0x300B2014 to 0x300B2017 : MII_RT_TXCFG1 Register Regards, Aaronhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692109/tms320f2806-request-proposal-for-traction-controller-solutionFri, 23 Oct 2026 05:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fedad89c-21dd-49f6-bfcf-afa238ed2d37SAGAR BHAVSARPart Number: TMS320F2806 Hello, Greetings of the day! We are currently developing an indigenous Motor Control Unit (MCU) for an electric Hub drive application with the following preliminary specifications: Rated Power: 3.3 kW Nominal DC Bus Voltage: 48 V (Nominal) Motor Type: BLDC/PMSM (FOC-based control anticipated) Communication Interface: CAN/LIN preferred Request to suggest the suitable & cost-effective solution from your portfolio along with following details: Recommended Microcontroller Part Numbers (PNs) suitable for the above application. Technical datasheets and application notes. Development tools and evaluation kits available. Unit pricing for prototype quantities and volume production quantities considering annual volume of 12000 pieces. Typical lead times. Roadmap and longevity information for the recommended devices. Kindly also suggest any reference designs or proven motor control platforms that can accelerate the development of motor controller. Additionally, if any evaluation board samples or ready-to-test solutions are available, we would greatly appreciate the opportunity to evaluate them, as they would help accelerate our prototyping and validation activities. We look forward to your recommendations.TMS320F2806https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691932/drv8220-request-for-alternate-part-for-obsolete-h-bridge-driver-si9986cy-t1-e3/6519271Fri, 23 Oct 2026 04:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5d369127-5bf9-4c58-abd9-d3f85b1dcec4Santhosh KHi Yao, Thank you for your response. Ideally, we are looking for a replacement IC with the same package, pin-to-pin compatibility, and identical truth table/functionality as the existing device. This would help us avoid PCB modifications and minimize validation efforts. Could you please suggest any available parts that meet these requirements? If a fully compatible replacement is not available, kindly recommend the closest alternatives and highlight any key differences. also attaching the snip of functional block diagram along with truth table for existing one. Thank you for your support. Best regards, Santhosh Kumarhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692102/drv8363-q1-drv8363-q1-clarification-on-uvlo-thresholds-ihold-csa-auto-zero-fault-modes-and-phase-diagnostics_2Fri, 23 Oct 2026 04:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0c2933b9-2b7e-4386-a6f8-d63b6e4535f7KIM SUBINPart Number: DRV8363-Q1 Q8. Relationship between VDS_LVL_x, SHORT_DET_EN, and the diagnostic status flags a) Does the automated short detection (SHORT_DET_EN = 1) use the VDS_LVL_x thresholds configured in MON_CTRL6, or a separate internal threshold? In other words, does changing VDS_LVL_x change the short-detection result? b) Are SHT_VDD_FLT_x and SHT_GND_FLT_x (IC_STAT3 [15:10]) set only while the SHORT_DET_EN sequence runs, or can they also be set during normal operation? Q9. Purpose of OFFLINE_DLY DIAG_CTRL1 OFFLINE_DLY [9:8]: 50 us / 250 us / 1 ms / 2.2 ms. a) What does this delay represent — the settling time after the diagnostic current is applied, before the comparator result is sampled? b) How should we choose the value? Which load characteristic determines it (phase node capacitance, motor inductance, cable length)? c) Does it apply per phase, or once per sequence? Q10. Phase diagnostic usage Section 6.3.6.14 describes the current sources and the status flags, but gives no recommended procedure. a) Could you provide a step-by-step procedure for the manual phase diagnostic (PH_DIAG_Hx / PH_DIAG_Lx) — what to set, how long to wait, which status bits to read, and how to interpret the result combinations to distinguish open load, short to battery, and short to GND? b) PH_DIAG_LL: “0h = PWM’ing allowed during phase diagnostic, 1h = No PWM’ing allowed during phase diagnostic.” What is the practical difference between the two, and what happens if the PWM inputs toggle while PH_DIAG_LL = 1? c) TCP_LL_MODE reduces the TCP switch current limit to 230 uA “for phase diagnostics.” Must this be set before running a phase diagnostic, and why? Q11. LOCK2 reset value a) Why is IC_CTRL_SP locked by default while the other control registers are not? b) Is the intended flow to write LOCK2 = 2h, change the settings (SPI_CRC_EN, DVDD_LVL, OTSD_MODE), and then write LOCK2 = 5h again? Is re-locking required or optional? c) Does LOCK2 protect only IC_CTRL_SP, or other registers as well? d) Are there restrictions on when IC_CTRL_SP may be changed — for example only in Standby mode, or only before the gate drivers are enabled? Thank you for your support.DRV8363-Q1https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692100/drv8363-q1-drv8363-q1-clarification-on-uvlo-thresholds-ihold-csa-auto-zero-fault-modes-and-phase-diagnosticsFri, 23 Oct 2026 04:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:15662087-c346-44e7-bc0b-45eeb51439c9KIM SUBINPart Number: DRV8363-Q1 Other Parts Discussed in Thread: DRV8363 Hi, We are designing a 48V three-phase BLDC drive with the DRV8363-Q1 in 6x PWM mode. While preparing our register configuration document I found several items I could not resolve from the datasheet. Q1. VGVDD_UVLO — two rows with identical parameter descriptions In Section 5.4 (Protection Circuits), VGVDD_UVLO appears twice: 5.35 / 5.65 / 5.95 V 5.25 / 5.55 / 5.85 V Both rows carry the identical description “GVDD undervoltage lockout threshold” with no test condition. All neighboring parameters (VGVDD_UV_BST, VGVDD_UVH, VGVDD_OV) explicitly state “rising” and “falling.” Is the first row the rising threshold and the second the falling threshold? Q2. Clarification on IHOLD and ISTRONG Functions and Current Behavior a) What are the precise functions and definitions of IHOLDand ISTRONG? b) Does the IHOLD(or ISTRONG) current value remain continuously supplied/maintained throughout the entire ON (or OFF) state period, or is it applied only as a transient pulse/pulse-width? Q3: CSA_AZ_TMAX and CSA_CLK I have read the earlier thread “DRV8363: CSA/AZ Register Clarification,” where it was explained that the auto-zero uses a ping-pong architecture with two amplifiers that alternate on rising edges and calibrate on their off cycle. Some points are still unclear. a) What exactly is CSA_CLK? The term is not defined anywhere else in the datasheet. b) During normal PWM operation, which edge triggers the ping-pong toggle — INHx, INLx, any phase, or an internal signal? c) What does CSA_AZ_TMAX = 3h (“No delay”) do? d) The CSA_AZ_DIS description says “Refer to timing requirements if this bit is used.” Where are those timing requirements? We plan to set CSA_AZ_DIS = 1 only while the MCU measures the zero-current ADC offset at standstill, then clear it. Is that the intended usage, and how long must we wait after clearing the bit before the CSA output is valid again? Q4. “Default mode” in the monitor mode fields Several monitor mode fields contain settings named “Default mode”: Register Field Codes MON_CTRL1 [10:8] VDRAIN_OV_MODE 4h, 5h, 6h MON_CTRL3 [15:14] VDS_MODE 2h MON_CTRL3 [7:6] VGS_MODE 2h MON_CTRL2 [4:2] SNS_OCP_MODE 5h, 6h MON_CTRL5 [2:0] BST_UV_MODE 6h What behavior does “Default mode” actually produce? Is it identical to the 0h setting (Warning, latched), or is it a reserved code that should not be used? Q5. VDRAIN_UVL_MASK operation MON_CTRL2 [14]: “If active it masks VDRAIN_UVL during first power-up sequence.” a) What defines the “first power-up sequence” — from nSLEEP rising until the device reaches Active mode, or until some other event? b) Does “mask” mean the VDRAIN_UVL status flag is not set at all, or that the flag is set but the configured response is not taken? Q6. SNS_OCP_TRETRY timing definition MON_CTRL2 [5]: “Sense OCP retry time, 0h = 1 ms, 1h = 9 ms.” There is no timing diagram for this parameter, so we cannot tell what it measures. a) Which two events does this time span — from SNS_OCP detection (or from gate shutdown) to automatic re-enable of the gate drivers? Q7. Clarification on Offline Open-Load Detection and Short Detection a) Offline Open-Load Detection: Under what conditions and through what mechanism does offline open-load detection operate? (Specifically, how is the open-circuit condition of a winding diagnosed when the motor is at standstill, and what are the detection criteria?) b) Short Detection: How are shorts distinguished and detected between normal switching operation and offline (standstill) conditions, and what mechanism does each use?DRV8363-Q1DRV8363https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691924/drv3946-q1-drv3946-peak-and-hold-current-regulation-not-reaching-configured-values/6519250Fri, 23 Oct 2026 04:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:14297e09-f484-4db0-80df-4f6706b0a006Debarpan BoseHello, the RIPROPI resistance is 10Kohms. Thanks, Debarpanhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1691647/mcf8329a-evaluation-board-altium-library-access/6519242Fri, 23 Oct 2026 04:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f3faa8d5-83db-4b83-a05d-fb5f4d25fd19DhineshHi Michael, I will generate the footprint library from the EVM layout file and share it with you. Regarding the active deceleration entry limit of the MCF8329HS, unfortunately we can't change the ACTIVE_BRAKE_SPEED_DELTA_LIMIT_ENTRY threshold minimum limit. Thanks, Dhineshhttps://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/1692097/drv8353rs-evm-all-mosfet-gate-pulses-disappear-after-approximately-1-06-s-when-nfault-goes-low-but-vm-uvlo-does-not-appear-to-triggerFri, 23 Oct 2026 04:01:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f5e2658f-377a-401e-b403-986bf220e8a4Aman ChaudharyPart Number: DRV8353RS-EVM Hello TI Support Team, I am testing a three-phase motor-driver circuit using the DRV8353RSRGZR gate driver. The schematic is designed according to the datasheet. 1. Observed issue HMC_0.0.0_SCH (1).pdf The gate driver powers up, and the supply voltages appear to be correct. PWM signals are initially present, and the gate-driver outputs generate pulses for all MOSFETs. After approximately 1.06 seconds, the nFAULT signal goes LOW. When nFAULT goes LOW, the gate-drive pulses disappear for all MOSFETs. I have checked the VM supply and have not observed an obvious undervoltage condition that would explain the shutdown. I am unable to determine which protection mechanism is causing the driver to stop switching. 2. Oscilloscope observations nFAULT Siganl OUTPUT GATE PULSE I have attached two oscilloscope screenshots showing the signal before and around the event. In the first screenshot, the displayed signal has approximately: Frequency: 10 kHz Period: 100 µs Peak-to-peak voltage: 10.7 V The second screenshot shows the cursor measurements around the event. I will verify the exact timing and signal identity during the next measurement. 3. Questions for TI What are the possible reasons for all six gate-drive outputs becoming inactive when nFAULT goes LOW, even if VM remains above the UVLO threshold Which SPI status registers and fault bits should I read immediately after the fault occurs to identify the exact cause? Is there a recommended procedure to distinguish a VM UVLO event from a charge-pump/regulator undervoltage or MOSFET overcurrent event?HybridDRV8353RS-EVMelectric & powertrain systems