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Part Number: DRV10970
According to the datasheet of DRV10970, it is mentioned that during sinusoidal mode of operation the PWM cannot go below 10%. Does the same apply for the trapezoidal mode ?
Hello Ruchitha Reddy,
The minimum 10% duty cycle (visualized in Figure 18: Duty Cycle Profile in the datasheet) is the same for both PWM and Trap control.
I do understand how that could be confusing since the text is in the Sinusoidal Pulse Wide Mdoulation Control mode section instead of a broader section that addresses both. We'll look into changing this in the future.
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In reply to Cole Macias:
Thank you for your quick reply.
Is it possible in any way for me to take a look at the test results for these two modes when pwm is below 10%? It would be a great help.
Also regarding the UVLO mechanism, does it take into consideration VM or VINT as it isn't clear enough in the datasheet? Any way I can get the architecture of the uvlo mechanism?
In reply to Ruchitha Reddy:
No problem, glad to help.
As for UVLO, yes, VM and VINT are considered for UVLO, I've attached their specifications from the datasheet below:
UVLO looks if the voltage on VM or VINT is less than the UVLO falling threshold. If the voltage is below the threshold for some amount of time, then the device will shutdown and stop driving the motor. The device will stay in this state until the voltage is greater than the UVLO rising threshold for some amount of time. Hopefully, this explains how UVLO works.
As for testing two modes below 10%, the digital blocks that sense the PWM input and determine whether Trap or sinusoidal is used, are seperate. To reiterate, the PWM takes the duty cycle and translates it into a speed command percentage. This speed command only determines the duty cycle when shaping the sinusoidal or trap signal, not the actual shape. As a result, the shape of waveform is independent of the duty cycle output. Feel free to use a DRV10970EVM to verify.
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