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DRV8432: DRV8432: OTW hysteresis

Part Number: DRV8432

Dear experts,

we are using DRV8432 in parallel mode at maximum power. To handle the thermal issues, we have attached a system of heatpipe and fan.We are in succsessful in mass production since almost three years. Actual we recognize an extended number of OTW warning events during device qualification tests.

As the maximum load is pulsing two times a second, The temperature of the chip seems to swing quickly. We realized that the OTW event does happen and resets after 100-200ms. With thermal hystersis of 25°C it suprises me that chip and heat system is able to cool down and reset OTW event so quickly. Is that thinkable? It depends much on the internal design and the thermal connection between sensor and MOSFET, does it? Or is it a proof, that the heat system is mounted not sufficent to the chip?

In ambient temperature, how quickly might the chip cool down without any cooling system? What are typical cooling times values e.g on the evaluation board?

Thanks and best regards,

Sebastian

  • Sebastian,

    1. The thermal shutdown recovery time is related to the thermal resistance between IC and ambient.
    2. During motor start-up, the winding current could be higher than a normal operation. That could can quickly heat up the IC.

    Your board thermal resistance and test load condition could be much different than an EVM board. But, the following analysis can help us understand: the heat sink is sufficient or not if we trust the IC temperature sensing. That can also tell us the power dissipation difference and heat sink difference could affect test result a lot. So, the EVM test may not cover or help your application. (BTW, I don't have EVM recovery time data. )

    “ the OTW event does happen and resets after 100-200ms”, if we assume the board temperature doesn't change very much in 100~200ms,
    a. that would tell us board temperature is below the recovery temperature (Tboard<Trecovery) . So, the IC can quickly resets after 100-200ms.
    b. when the thermal shutdown is triggered, the silicon temperature reaches the thermal warning triggering point OTW.

    According to a and b, we can get Tboard<Treovery=(OTW -25C). 25C is the OTW hysteresis. So, Tboard < OTW -25C. The board temperature is below silicon OTW temperature at least 25C. Also, the datasheet shows 0.9C/W junction-to-case (power pad / heat slug) thermal resistance. Now, if we can estimate the power dissipation of DRV8432, we can know the heat sink is good enough or not.

    For example: if DRV8432 power dissipation is 3W and the junction to board or heat sink temperature is higher than 25C, the total thermal resistance is about 25C/3W= 8.3 C/W which is much higher than IC's 0.9C/W junction to case thermal resistance. I would say the heatsink or its installation may not be good enough.
  • Dear Wang,
    I'm aware of that our system is designed with not much temperatur gap to the top.
    But we have been successfully producing almost thousand units without a problem.
    We did have change the test procedure not long ago: The system has been tested in climatic chamber at 45°C, now we test at room temperature (about 25°C) but with higher load. Nevertheless, the average temperature on the PCB nearby DRV8432 after one hour testing has been reduced by the amount of about 5°C (before about 100°C, now 95°C). Therefore I would have assumed to have also lower probability to see OTW alarms. We did not change any relating components, only the mounting personal has been changed.
    But since short time we do have several units with many short timed OTW-peaks, sometimes OTW+over temperatur shutdown.
    I only find the explanation in the way of mounting. But sadly I dod not find the problem in mounting.
    I was surprised of this quick change of temperature especially the cooling down - and I assume to have a proof that there is a bug in mounting. That's why I posted.
    But sadly till now I do not really find the place where to improve.
  • Sebastian,
    Would you try some grease thermal paste to improve the thermal conductivity? I would think at least it can prove install correct or not.
  • Dear Wang,

    we already are using very high quality phase shift material, which has been printed on the opposite part. I assume, the internal thermal resistance of the chip is quite high. As we are working close to the limit and due to the wide spreaded R_DSON of the chip, we will always will have better and worse parts. And with high load differences, a quick toggle of the OTW pin might be unavoidable.

    I think we can close the issue in the E2E Community, even if my problem is not totally solved. Either we will have to live with the OTW or we have to change the chip.

    Thanks for you help, best regards,

    Sebastian