This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8323: Schematic Review

Expert 3020 points

Replies: 3

Views: 541

Part Number: DRV8323

Moving DRV8323H schematic review email discussion onto e2e for support.

We are evaluating DRV8323H gate driver to be used in our BLDC motor controller module. First, we got and played with a couple of BOOSTXL-DRV8323RH. That went smoothly.  Now, we are testing it on our own  prototype board with the more powerful MOSFETs.  On the multiple boards,  the DRV8323H has been blowing out suddenly.  Schematic shared offline.

Also I would like to find out if is allowed to swap the SPx and SNx pins in order to have positive amplifying network gain.

Product line response: Yes, you can flip the SPx and SNx.

Questions regarding the design:

How much current load is there and how much current is expected?
Customer: 15Amax continues

I see Vds monitoring is off (3v3 to VDS pin).
Customer: Yes, this has been done intentionally. Is there any problem with doing that? 

Situations, where the DRV can blow up, can be due to voltages being outside of device ratings. The device, per se, does not see currents.
Customer: We have measured voltage levels on all PWR and control pins to make sure they are correct. 

If possible, please ask for an image of where the blow occurs to know what pins it stems from.
Customer: We can send an image, but it won’t be showing anything. There is no visible damage on the IC.  After the DRV8323H is damaged the gate driver’s outputs are always 0V while the PWM is present on the inputs.

Is there a fault asserting before the blow?
Customer: We are still investigating this matter, but so there is not a fault asserting detected before the blow.

SPx and SNx can be flipped, although it will cause the low side VDS monitoring to include the sense resistor voltage.
Customer: If the VDS monitoring is disable, would it be safe to flip the SPx and SNx to have positive amplification gain?

Has the DRV operated successfully lower IDRIVE values?
Customer: We tried minimum configuration of IDRIVE (10/20mA). The gate signals were destroyed. This might be because our PWM frequency is 30kHz due to the low inductance (0.3mH) of the motor. 60/120mA IDRIVE and 0.26V VDS are the latest configuration that we are using. 

15A max continuous expected? Is that the current seen?
Customer: A motor under test is 250W nominal power at 36V. Although it should be 7A we measured up to 16A maximum continues current while the motor was under extreme load.   


Product line recommendation:

I wanted to point out that, since the customer is utilizing parallel FETs in their design, we have seen design issues before with improper circuit configuration with parallel FETs. The customer can use the following TIDA-00774 as a reference to parallel FET system design. The Design Guide’s section 6.2.1 goes into detail as to what to consider when designing parallel FET applications.

www.ti.com/.../TIDA-00774

Of note are the gate resistors added to each parallel FET and the placements of these resistors, the decoupling capacitors, the power layout copper pours, and the FETs.

This post has been shared with the customer to continue the schematic review discussion here.

3 Replies

  • Hi Chuchen,

    Can customer provide a complete schematic? It can sent offline.

    Additionally, is the VM voltage being monitored? Can they provide scope captures?

    Where is the 16A max continous being measured?

    Are there any bulk capacitances on the VBAT input?

     

    Hector Hernandez
    Motor Applications Team

  • In reply to Hector Hernandez Luque:

    Hi  Hector/Chuchen,

    The schematic has been sent to Chuchen  offline. 

    VM voltage is steady. 

    16A is measured at VBAT input.

    There is 1000uF electrolytic and 1uF film capacitors on the VBAT input. 

    Regards,

    Ash

     

  • In reply to ashavet:

    Hi Ashavet,


    Have you tried to spin this motor with only one of the parallel FETs on each bridge?

    Have you verified your parallel fet design with the guidelines suggested in Section 6.2.1.2 Switching Phase of the parallel fet app note? Of most important note is using the gate resistors in front of the parallel FETs.

    When you used the EVM, did you try to spin the same motor at these driver settings?

    In the end, I want to see if you can work your application without a parallel FET solution. It introduces a lot of variables to the GHx, Glx, and SHx lines. The possible issue I see is the GHx magnitude being at 36 V + 10 V = 46 V. This value is close to the 60 V abs max. If there are transients or coupling due to the voltage differences introduced with parallel FETs, it could violate the abs max.

    Also, how did you calculate the bulk capacitance of your system?

     

    Hector Hernandez
    Motor Applications Team

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.