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DRV10866: FG output and Lock detection

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Shunsuke Nagata

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Part Number: DRV10866

Hi,

I'd like to know the FG output and Lock detection feature of DRV10866.

1. Depend on customer application and environments, the DRV10866 cannot detect the point BEMF cross zero due to noise.
In this case, how will FG output be? I guess FG out may not output in this case. Is it correct?

2. Could you please let me confirm about the www.ti.com/.../slva612a.pdf document
My understanding for the explanation is if internal sampling clock of external system such as MCU is 101.6Hz, the system may detect as rotor is locked even if FG is working. Then, the sampling clock of external system should be 2X from 101.6Hz. Is my understanding correct?

Nagata.

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Sanmesh Udhayakumar
- Mar 1, 2019 11:13 PM
Hello Nagata-san,

1) I have to confirm this, but I believe, it BEMF zero-crossing is being missed due to noise, the FG will stay in its current state (either Hi-Z/Hi_if_pulled_high or GND) and not switch. If fg doesnt switch within lock detect time,, the device will hit lock rotor detection. Let me confirm this.

2) I think your understanding might not be correct. The FG pin is associated with the speed of the motor. If you spin the motor at a multiple of the DRV10866 sampling clock freq(101.6Hz), the FG signal should have the frequency of a multiple of the DRV10866 sampling clock freq(101.6Hz). If this happens, then you may falsely detect the FG signal isnt changing state and thus falsely trigger a locked rotor condition. visually you can see this below:
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Sanmesh Udhayakumar
- Mar 4, 2019 11:40 PM
In reply to Sanmesh Udhayakumar:

Yes I can confirm this answer. Please let me know if I answered all your questions.
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Shunsuke Nagata
- Mar 5, 2019 2:24 AM
In reply to Sanmesh Udhayakumar:

Hi, Udhayakumar -san,

Thank you for your supports.
Could you please let me confirm about 2)?

If the FG running with 101.6 Hz which is same frequency as internal sampling clock, the lock will be detect within about 3 sec. Is my understanding correct?

Regards,
Nagata.
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Shunsuke Nagata
- Mar 5, 2019 10:17 AM
In reply to Shunsuke Nagata:

Hi, Udhayakumar -san,

Here is additonal question for 2). If my understanding is correct, is there soluton not to occur the falsely locked motor detection? Is the only method to protect the falsely detection that FG signal should be multiple of internal sample clock?

Regards,
Nagata.
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Sanmesh Udhayakumar
- Mar 6, 2019 2:26 PM
In reply to Shunsuke Nagata:

Question: "If the FG running with 101.6 Hz which is same frequency as internal sampling clock, the lock will be detect within about 3 sec. Is my understanding correct?"
Answer: It will detect within whatever the "Lock detect time" spec is in the datasheet.

Question: "If my understanding is correct, is there soluton not to occur the falsely locked motor detection? Is the only method to protect the falsely detection that FG signal should be multiple of internal sample clock?"
The methods to protect against false lock detection are in this document www.ti.com/.../slva612a.pdf
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Shunsuke Nagata
- Mar 6, 2019 3:06 PM
In reply to Sanmesh Udhayakumar:

Udhayakumar -san,

If FG run at 1/2 internal clock freq, is it possible to protect false lock detection?

Regards,
Nagata.
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Sanmesh Udhayakumar
- Mar 7, 2019 3:57 PM
In reply to Shunsuke Nagata:

Yes. If internal clock frequency is 2x faster than FG, then you will detect the high and low of FG.
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Shunsuke Nagata
- Mar 8, 2019 9:56 AM
In reply to Sanmesh Udhayakumar:

Udhayakumar -san,

Could you please check each below condition:
(Let me use 100Hz for sampling clock freqency instead of 101.6Hz to simplfy the explanation.)

Case 1: FG = 100Hz
- Sampling clock = 100Hz and FG = 100Hz : False lock detection will be happend
- Sampling clock = 100Hz and FG = 50Hz(1/2 x 100Hz) : False lock detection will NOT be happened

Case 2: FG = 200Hz (Even multiple of 100Hz)
- Sampling clock =100Hz and FG = 200Hz : False lock detection will be happend
- Sampling clock =100Hz and FG = 100Hz(1/2 x 100Hz) : False lock detection will be happend

Case 3: FG = 300Hz (Odd multiple of 100Hz)
- Sampling clock = 100Hz and FG = 300Hz : False lock detection will be happend
- Sampling clock = 100Hz and FG - 150Hz : False lock detection will NOT be happened

Are above my understanding correct?

Regards,
Nagata.
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Sanmesh Udhayakumar
- Mar 11, 2019 4:16 PM
In reply to Shunsuke Nagata:

Yes
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Shunsuke Nagata
- Mar 12, 2019 8:28 AM
In reply to Sanmesh Udhayakumar:

It seems that DRV10886 detect lock detection falsely during changing PWM. Is it possible to disable lock detection?

Regards,
Nagata.
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