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Original question:

DRV8350: DRV8320 - Gate Driver and possible Charge Pump Failure

DRV8350R: Gate driver failure

Eduardo Garcia Lopez
Prodigy 140 points
Part Number: DRV8350R
Other Parts Discussed in Thread: DRV8350

We have designed a speed controller for BLDC motors based on DRV8350 and we have been experiencing pretty much the same problem described in [1].
We started working with the hardware version of the DRV8350 and after having six units destroyed during the testing we changed to the SPI version which is more versatile and let us check the cause of the faults. With the SPI version we adjusted the lowest value for the gate currents (IDRIVE) that avoids ringing (300mA/600mA), but even though it took more testing time to get into troubles than with the H version, we are still finding the same problem as described in the [1] post: while the motor is spinning the driver suddenly fails with GDF fault condition in Fault Status Register 1, and at least one of the VGS_XY fields set on Fault Status Register 2. When we measure the Zout of the gate drive indicated in Fault Status Register 2 we always find that the Zout of that specific gate drive (as measured from the GLX pin of the DRV8350S to ground) is too low (sometimes zero) instead of around 140k.

VM is 12V, and the VDrain of the MOSFETs is 67V. The MOSFETs are 12 x IPT015N10N5. We have tested both synchronous and asynchronus rectification (controlled by firmware, the DRV8350 was always in 6x PWM mode) with the same results, and PWM frequency has been 16kHz, 32kHz and 48kHz, in all cases we found the failure.

Unfortunatelly the mentioned thread, even though closed as "resolved" did not display a solution to this problem, this is why I am opening this new thread.

[1] https://e2e.ti.com/support/motor-drivers/f/38/t/735873

  • 0
    TI__Guru 61380 points
    Eduardo,

    How much Qgd is present on each GHx and GLx? What is your required rise and fall times of your gate signals?

    What is the width and length of your gate/SHx traces?

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 140 points

    Adam,

    the Qgd on GHx is 2 x 51nC maximum, and the same for GLx.

    Regarding slew rate, the required rise time is <400ns (which is > Qgd / Idrivep = 340ns), and the required fall time is <250ns (which is > Qgd / Idriven = 168ns).

    We want to work with PWM from 10% to 100% at 32kHz, so the width of the gate/SHx pulses range from  3.125us to 31.250us.
    With the scope we can see the low side gate voltages pulsing between 0V and 11V and the high side between VDC and VDC + 8V.
    The phase voltages look correct too, 0V to 67V (VDC) following the gate control signal. 
    Everything looks correct until the gate drive, for unknown reason, gets destroyed.

    Let me know if you need some scope traces.

  • 0 in reply to Adam Sidelsky
    Prodigy 140 points

    Hi again Adam,

    now I realize that I missunderstood your last question about traces.

    The tracks are 0.25mm wide all of them, and the lengths range from 10mm to 65mm.

  • 0 in reply to Eduardo Garcia Lopez
    TI__Guru 61380 points
    Eduardo,

    Thanks for the info. I would agree that your IDRIVE settings are correct, I always check because most customers just drive it as hard as they can which is incorrect.

    Trace widths are correct as well.

    Some of our customers who use parallel FETs use gate resistors to help match the gate impedance and prevent ringing between the two FETS, have you tried this? This is especially true at higher VM voltages.

    Can you share your layout?

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 140 points

    Adam,

    I had gate resistors in the initial design, but I removed them because I thought they could interfere with the Smart Drive feature of the DRV8350. I will re-add them (I think 4R7 will work) and will test.

    Also I am going to add a 1k gate to source resistor, at least on the low sides, to avoid drain to gate coupling, as I have seen some high frequency spikes on the low side gates when the high side MOSFET turns on. The 140k of the DRV8350's gate drive output is too high for those high frequency spikes.

    I'll let you know the results.

    Thanks for the support,

    Eduardo

  • 0 in reply to Eduardo Garcia Lopez
    TI__Guru 61380 points
    Eduardo,

    Thanks! Can I close this thread for now?

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 140 points

    Hi Adam,

    sorry for the late answer, it was not until today that I could finish the testing
    I have tested two configurations with the same results: the DRV8350 gets permanently damaged after some minutes testing.
    In the first configuration I added Rg of 4R7 and Rgs of 10k.
    In the second configuration I just removed the parallel MOSFETs, just leaving one MOSFET per side (six MOSFETs total).
    In both cases I had the same problem.
    The error reported via SPI is 0x0500 in Fault Status Register 1 and 0x0004 in Fauilt Status Register 2. This indicates "gate drive fault condition", specifically gate drive fault on the B low-side MOSFET.
    When I measure the gate drive's Zout of the B low side MOSFET on the DRV8350 it has low impedance, 40k instead of 140K.
    All the other gate drive impedances are correct, 140K.
    The VDRAIN during these tests was as low as 28V, and I was using a lab power supply with current limited to 1.5A, but the current on the MOSFETs never went above 750mA.

    Do you have any suggestion?

  • 0 in reply to Eduardo Garcia Lopez
    TI__Guru 61380 points
    Eduardo,

    Were you able to check for ringing on the gate lines after you added the resistors?

    Can you share your schematic and layout?

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 140 points

    Hi Adam,

    unfortunatelly I had no chance to check the ringing before the drivers were damaged, I .
    I have ordered more DRV8350RS, as soon as I get them I will retest and will try to measure the ringing, before and after adding the Rg.

  • 0 in reply to Eduardo Garcia Lopez
    Prodigy 140 points
    And yes, I can share the schematics and layout, but I would have to do it privately.
  • 0 in reply to Eduardo Garcia Lopez
    TI__Guru 61380 points
    Please add me as a friend on E2E and then you can send me the files privately.
  • 0 in reply to Adam Sidelsky
    TI__Guru 61380 points
    Eduardo,

    We usually recommend against having the FET and DRV on seperate boards. The added inductance and impedance can cause a lot of gate ringing which may damage the DRV.

    Have you checked for ringing on the GHx/GLx/SHx lines near the DRV?

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 140 points

    Hi Adam,

    I just received new DRV8350RS to replace the broken ones, as soon as I rework the boards I will re-test and will let you know what I find regarding the ringing on the gates.

    Regards,

    Eduardo

  • 0 in reply to Eduardo Garcia Lopez
    TI__Guru 61380 points
    Eduardo,

    If you do not have it now, please add bulk capacitance between the VDRAIN and GND of the FETs as close to the FETs as possible. This would help suppress any voltage spikes that the FETs may be having.

    Regards,

    -Adam
  • 0 in reply to Adam Sidelsky
    Prodigy 140 points

    Hi Adam,

    first, thanks for the sugestion, I already had bulk capacitors, 8800uF total in the board with the MOSFETs.

    And second, I have found that ringing could be the cause of the gate drive being destroyed, even when using just one MOSFET per half-bridge, but not where I had expected to find it. I found that the falling edge of the high side gate voltage caused ringing, making the voltage of the high gate to drop some volts below zero (as much as -11V sometimes) for some dozens nanoseconds. I think this is out of specs for "High-side gate drive pin voltage with respect to SHx (GHx)" that is -0.3V and for  "Transient 200-ns high-side gate drive pin voltage (GHx)" which is -10V.
    When I change the IDRIVEN_HS value from the 600mA that I was using before to the minimum value of 100mA, even with no gate resistance, I found that the problem dissappears, so I think that this ringing the reason of this problem.

    I have redesigned the board to have one independent rgate for each MOSFET, as soon as I get the new boards I will retest, but I think that this problem has been already fixed.

    Thank you very much for your help,

    Eduardo.

  • 0 in reply to Eduardo Garcia Lopez
    Prodigy 140 points

    Hi again Adam,

    update: I have just burnt another driver, this time with the lowest possible value for IDRIVEN_HS, 100mA, and with just ONE MOSFET per cell.
    In fact I found that one of the MOSFETs, the one in the high side of the phase C half-bridge, had been destroyed too, drain and source shorted, what makes me think that a shoot through took place.

    I wonder if the scope's probe is contributing to this problem, as I can see always that the destroyed gate drive is the one in the C phase, that is where I put the scope's probe.

    Also the voltage is contributing for sure: when I test at 24V everything seems to be working fine.

  • 0 in reply to Eduardo Garcia Lopez
    TI__Guru 61380 points
    Eduardo,

    How is the scope probe connected?

    For example where is the GND connected?

    Regards,

    -Adam