Hi all
Would you mind if we ask DRV8881E?
Please refer to the attachment file.
20190423_DRV8881E_question.pdf
Kind regards,
Hirotaka Matsumoto
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Hi all
Would you mind if we ask DRV8881E?
Please refer to the attachment file.
20190423_DRV8881E_question.pdf
Kind regards,
Hirotaka Matsumoto
Matsumoto-san,
During the sleep mode, DRV8881 has to hold the high side FET off. DRV8881 internal high FET gate drive circuit may have a leakage path to ground to hold high FET off. When the VM voltage is higher than a certain high FET gate voltage threshold, the leakage path is active.
I am going to confirm it with a designer. On customer side, they can reduce the VM voltage to 20V or 15V to see the leakage current change.