[FAQ] Selecting the Best IDRIVE setting and Why this is Essential

Using the wrong IDRIVE setting can damage your FET or DRV as it often causes excessive ringing and/or cross-conduction when the Gates are slammed on or off too strongly. This document discusses the methods and some Do's and Don'ts

IDRIVE Do's and Don'ts

DO:

• Calculate your IDRIVE setting based on the section below.
• Start from lower IDRIVE and slowly work your way higher. This prevents device damage such as cross-conduction and output ringing because the IDRIVE is too high.
• Check your switch node and gate lines using a scope to make sure the FET is getting fully turned on and there is minimal ringing on the lines due to overshoot and undershoot.

DON'T

• Use Max IDRIVE because my system must switch in 1nS. Often times this is impossible, not necessary, and dangerous to the longevity of the FETs and DRV.
• Increase the IDRIVE higher than the point you see excessive ringing on the switch node or gate lines. Increasing IDRIVE will make this worse unless you are way way too low on IDRIVE. Calculate your IDRIVE based on the section below and go from there.
• Use gate resistors unless they are required by your design. Gate resistors will complicate the IDRIVE setting and are usually not needed unless a safety or automotive requirement exists.

How Do I Select the Best IDRIVE For My System

Configuring IDRIVE for an exact FET part number is essential to the well tuned operation of the system. This tuning balances Thermal performance with Device performance while ensuring longevity of your DRV and FETs. To best select IDRIVE settings, please follow the following steps:

1. Find your FET part number and associated datasheet.
2. Locate the Qgd value in the datasheet. The typical Qgd is acceptable but always be aware of the min/max/tolerance of the Qgd.
3. Estimate your needed phase Rise and Fall time. For many customers between 100nS and 300nS is acceptable

Use the following equation to calculate the needed IDRIVE current in mA (rise and fall use the same equation):

1. Qgd (nC) / Trise (nS) = IDRIVE (mA)
2. Example: 14nC / 100nS = 140mA.

• We should therefore select the 120mA or 160mA setting for IDRIVE.

Concerning multiple FETs in parallel: When more than one FET is used per gate output (2/3/4/etc. FET in parallel, often used to reduce current handling per FET for the same phase or to reduce effective RDSON) this equation needs to take into account the TOTAL Qgd represented by all FETs on the gate output of note. If excessive gate ringing cannot be avoided through IDRIVE adjustment, the FET-to-FET parasitic mismatch may be too much and series gate resistors of up to 20 ohm can be used to smooth gate signals. IDRIVE will need to be higher if gate resistors are added.

Summary: The goal of the correct IDRIVE setting is to allow fast switching of the FET so that the resistive region of the FET is limited while also preventing ringing of the switch node and gate signals. Driving the gates too hard can damage the FET, DRV, or cause excess ringing and noise in the system. If this IDRIVE setting is too low and not fully enhancing the FET, the FET and DRV may undergo unnecessary heating. To resolve this, the IDRIVE can be increased one or two settings higher until better enhancement is reached but not so much that ringing is caused.

Further Reading and Source: http://www.ti.com/lit/an/slva714c/slva714c.pdf

Regards,

-Adam