DRV8833: About Internal Dead Time

Hi,Rick.

Thank you for your reply.

I would like to ask one more question.

According to Datasheet p.12, It is written below contents.

As mentioned above, is it correct to recognize that "The internal dead time" in this sentence is the dead time between high-side and low-side FET as well as the first question?

I would appreciate it if you could get back to me right away.

Best Regards,

Y.Ottey

Hi Y.Ottey,

Yes; "The internal dead time" in this sentence is the dead time between high-side and low-side FET as well as the first question.

The input to output propagation delay is matched such that the outputs are not in opposite states.

Hi Rick,

Thank you for your reply.

Assuming that “the internal dead time” is the dead time between high-side and low-side FET as well as the first question, “cross conduction(shoot through)” in below contents represent shoot through flowing from AOUT1 to AOUT2 (BOUT2)?

Best Regards,

Y.Ottey

Hi Y.Ottey,

Yes that is correct. In parallel mode, there are two paths that are protected by the dead time.

1) Standard shoot through from the high side to low side of an output. This one is true for non-parallel mode also
2) A shoot through where one OUT pin has switched low or high while the other OUT pin has non yet been disabled and is driving high or low.

Hi Rick,

Thank you for your reply.

I would like to ask more questions about your answer below.

1.I recognize that the following "shoot-through" is a shoot-through that flows from AOUT1 to BOUT1 when Parallel Mode.

2) A shoot through where one OUT pin has switched low or high while the other OUT pin has non yet been disabled and is driving high or low.

Is this recognition correct?

2.As for the protection against the second shoot-through on your previous answer, is the protection of only the dead time of the upper and lower FET at 450ns described in the data sheet?

In addition, in this case, is it protected by dead time within the specified dead time (450 ns)?

3.Does the protection by internal dead time in "Typical Application" on p.12 assume that there is no deviation between the AINx and BINx input signal?

Is there a possibility that shoot-through may flow when the signals to AIN1 and BIN1 are input with a gap of 450 ns?

Regards,

Y.Ottey

Hi Y.Ottey,

I would like to ask more questions about your answer below.

1.I recognize that the following "shoot-through" is a shoot-through that flows from AOUT1 to BOUT1 when Parallel Mode.

2) A shoot through where one OUT pin has switched low or high while the other OUT pin has non yet been disabled and is driving high or low.

Is this recognition correct?

>>> Yes, your recognition is correct.

2.As for the protection against the second shoot-through on your previous answer, is the protection of only the dead time of the upper and lower FET at 450ns described in the data sheet?

In addition, in this case, is it protected by dead time within the specified dead time (450 ns)?

>>> Yes, both the upper and lower FET shoot-through and parallel mode shoot-through cases are protected within the 450ns. The parallel mode case assumes the inputs are connected at the inputs.

3.Does the protection by internal dead time in "Typical Application" on p.12 assume that there is no deviation between the AINx and BINx input signal?

Is there a possibility that shoot-through may flow when the signals to AIN1 and BIN1 are input with a gap of 450 ns?

>>> Yes, this assumes there is no deviation between the AINx and BINx signals. Yes, there is a possibility of shoot-through if the gap exceeds the dead time.