DRV10866: FG Jitter and using it to phase lock

Russell Wetherley1

Part Number: DRV10866

Hello E2E,

I have a question in regards to using the FG pin on the DRV10866.

Is the FG signal derived directly from BEMF detection (some analog comparator output) or is it gets synced to an internal clock?

The reason for the question is we would like to phase lock the motor to another system within 1us of phase jitter - is the FG signal usable in the feedback loop as a reliable proxy for motor position?

If it gets 'reclocked' which results in the FG signal being quantized by the internal clock, it will mess up the intended VCO control loops which are attempting to phase lock the two systems.

I realize this is a low cost fan driver part not probably not intended for this purpose and that there are drivers with 'true' back-emf signals - but would like to know if this is the case for the DRV10866 part. If this isn't possible with the DRV10866, can you recommend a similar part with this feature?

I did find this post, but it still left some questions unanswered.

Thank you!

Russell

over 4 years ago

0 Michael.Walker over 4 years ago

TI__Mastermind 19720 points

Hi Russell,

I am checking with our design team to make sure that the FG signal is not a clocked/gated zero crossing signal.

Regards,

Michael

0 Michael.Walker over 4 years ago in reply to Michael.Walker

TI__Mastermind 19720 points

Hi Russell,

Just to update this tread on the progress. Design is still working on it. I have made some initial measurements in the lab. I used a motor and probed the FG signal with a scope. The yellow signal is the FG signal

You can see that the motor speed is 268.9Hz and the standard deviation is 602 mHz or a period of 3.7ms with a standard deviation of 8us. This standard deviation could have been caused by the control loop varying the motor speed so I cannot say for certain that the FG signal is gated or not just yet. I will update once design comes back with an answer.

Regards,

Michael