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DRV8323: ENABLE signal: has this more functionality?

Part Number: DRV8323

Dear TI support forum,

thank you very much for giving me the possibility to post my question here.

I made a design with the DRV8323S, using the SPI interface to configure all parameters. Basically the schematics are similar to the evaluation board with

two major exceptions: I fixed the signals ENABLE to high (5V) and CAL to low. However, the high side gate driver signal is always about 24V with VM=24V,

independently from the input signals. The low side gate driver works as expected ( show 10V when activated ). DVDD shows 3.3V, the charge pump works and

the SPI interface works, too. I can set and read registers as expected.

My question: is it ok to fix ENABLE to high or is there a specific power up procedure like: "ENABLE low, then VM, then ENABLE high" or similar. It might be,

that ENABLE implies a kind of reset functionality, which is not given, if I fix it to high.

Thank you very much for your reply.

Daniel

  • Daniel,

    Thanks for posting on the MD forum!

    When measuring the High Side Gate are you measuring differentially from GHx to SHx? This is the voltage that controls if the FET is ON or OFF.

    Regards,

    -Adam

  • Hello Adam,

    thanks for your quick reply and sorry for being so fuzzy.

    Actually I measured against ground and have about 24V on GHx and SHx. As the drain is connected to VM it looks as everything around the high side MOSFET is at the same voltage level. My first assumption was that the MOSFETs have a defect, but that's not the case.

    In other words, measuring between GHx and SHx should give about 0V, which should be ok for a OFF signal to the FET. However, even if I apply a HIGH to the input signals, I see not differences on the output signals for the high side, namely the GHx signal. As mentioned, the low side works ok and as expected, the charge pump, too.

    Coming back to my original question: is it ok to tie ENABLE to high all the time or do I need to go through a disable/enable sequence with this signal?

    Regards

    Daniel

  • Daniel,

    When the High side is OFF, the GHx is shorted to SHx which prevents any Vgs from developing. There are some cases where a very small leakage path inside the device will show some voltage on the GHx/SHx when the high side is OFF but this will dissipate when the high side turns on and is used.

    If you are not using any low power mode and you are using the SPI device, you should be fine because you can clear faults using the CLR_FLT SPI bit.

    Have you checked if you have any faults?

    Did you try a second device?

    Regards,

    -Adam

  • Hello Adam,

    thanks for your kind reply. All your information are very helpful for me.

    Finally I got the device running. The condition, ENABLE always high, works as you have explained.

    Right now I got some faults for VGS and VDS, but that's another story.

    Thanks again for your kind and quick support.

    best regards

    Daniel