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DRV8353: Transient 200-ns high-side source sense pin voltage (SHx)
Part Number: DRV8353
I am currently doing board layout for a design which uses the DRV8353RS gate driver.
One thing that gets me a little confused, when digging through the part's datasheet, is the high-side gate current return path.
Looking at the layout guidelines (section 11.1) in the datasheet (quote): "...Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the low-side MOSFET source back to the SPx/SLx pins."
These recommendations on gate drive current loops seem pretty obvious for someone who has some experience with power electronics design and I totally agree concerning the low-side loop. I would also agree for the high-side loop if the DRV8353 would use "standard" bootstrap circuitry which is referenced to the according SHx pins. Now, what makes things a little confusing for me, is that the charge pump for the high-side driver supply is obviously referenced to VDRAIN (like it is shown in Figure 29). So, when a high-side FET is turned on, the necessary gate-charge is provided by a current which is drawn from the VCP capacitor (connected between VCP and VDRAIN). This means that the gate current flows out of the capacitor's VCP terminal - through the high-side driver - into the MOSFET gate - out of the MOSFET source - and where does it go now? Since the current needs to go back to the second terminal of the VCP capacitor, which is VDRAIN, there must be a path which allows the gate current to flow from SHx to VDRAIN. Looking at Figure 32 it don't see how this is achieved. I don't assume the current loop is closed through the high-side FET's body diode and the VDRAIN sense line - because that would be kind of awkward.
Since the gate drive current loop is a pretty critical topic, when it comes to board layout, I hope you can resolve my confusion.
Thanks and best regards,
Thanks for posting on the MD forum!
The VCP cap is referenced to VDRAIN and is used to store the VCP voltage above the VDRAIN level. The actual VCP voltage is formed from VM being switched under the CPH/CPL cap voltage (the charge pump top FET is turned on) which gets charged to the VDRAIN voltage when the lower FET of the charge pump is on.
This being said, the return path of the HS FET turn on is through the FET bridge parasitcs to GND and then back through the VDRAIN cap and back to the charge pump.
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In reply to Adam Sidelsky:
thanks for the quick response. I do understand the first part on how the charge pump regulates VCP to approx. VDRAIN + 10,5V.
Unfortunately I still don't get the second part about the HS FET turn-on. Is the required gate charge during turn-on drawn from the VCP/VDRAIN cap or from the CPH/CPL cap? Which parasitics are exactly involved? If you're saying that the current flows through parasitics to GND and then back to the charge pump, this would mean that the SHx pin is not involved (but rather the SLx Pin) during HS FET turn-on.
Is it maybe possible to get a quick and dirty sketch of the turn-on gate current loop (e.g. by scribbling into Figure 21.)?
Sorry for being so persistent...
In reply to Sebastian Ausserwoeger:
Yes you are correct, the SHx path is not involved in the HS turn on, it's used predominantly in the HS FET turn off.
The charge for the gate comes from both the CPH/CPL cap and the VCP cap as they are both connected from VCP to GND. Since the VCP cap is so much larger than the CPH/CPL cap, most of the charge comes from the VCP cap.
The FET parasitics mentioned are out to the motor, through the body diodes, and the PCB trace parasitics. In the end everything gets back to GND.
I don't have a diagram at this time but hopefully the above is more clear.
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