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DRV8323: failure analysis for stuck FET

Part Number: DRV8323

Did you analyze the probability and impact (in the component FMEA, etc.) of the failure mode of a stuck MOSFET gate signal, even when the DRV input is still driven by PWM signals from the SW.

In the datasheet the following statement is given:

“The third component of the TDRIVE state machine implements a scheme for gate fault detection to detect pin-to pin solder defects, a MOSFET gate failure, or stuck-high or stuck-low voltage condition on a MOSFET gate”.

Is there any certain design in the DRV which avoid a impact of a certain DRV failure (stuck output) into this kind of monitoring function (independency between theses features / functions)?

What is the argumentation to detect a stuck output (caused by internal failure) within the DRV mechanism…?

  • Guenter,

    The Vds monitors and Vgs monitors are separate from eachother and from the pull-up and pull-down FETs inside the DRV. This can be seen in these two images from the datasheet:

    Please let me know if this helps.

    Regards,

    -Adam

  • For the FMEA that we are running, it is key to know where the signals “High-Side Vds Monitor” and “Low-Side Vds Monitor” are connected.

    In case connected to the Digital Core of the driver, would be an issue.

    If digital Core hangs-up, it could occur MOSFETs do not respond to the InHx pins, and at the same time, Vds errors will not be recognized because they depend also on the state of the Digital Core.

    In case “High-Side Vds Monitor” and “Low-Side Vds Monitor” where directly connected to the Driver Error output pins, it would be possible to argument that the Driver is single failure tolerant.

    Please clarify & thanks a lot !

  • This post is continuing over email and will be updated here once complete.

    Regards,

    -Adam