Did you analyze the probability and impact (in the component FMEA, etc.) of the failure mode of a stuck MOSFET gate signal, even when the DRV input is still driven by PWM signals from the SW.
In the datasheet the following statement is given:
“The third component of the TDRIVE state machine implements a scheme for gate fault detection to detect pin-to pin solder defects, a MOSFET gate failure, or stuck-high or stuck-low voltage condition on a MOSFET gate”.
Is there any certain design in the DRV which avoid a impact of a certain DRV failure (stuck output) into this kind of monitoring function (independency between theses features / functions)?
What is the argumentation to detect a stuck output (caused by internal failure) within the DRV mechanism…?