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BOOSTXL-DRV8320RS: NexFET VDS leakage

Guru 54077 points
Part Number: BOOSTXL-DRV8320RS
Other Parts Discussed in Thread: DRV8320

Oddly when all output drives are low (off) the inverter phases are nearly at full VDS of supply (40v). Our other DC inverters using typical single NFETS have lower VDS leakage <3v. As the high side VDS increased >150vdc that same high FET VDS nears 10v-13v on the phases depending on the 1/2 bridge drive current. The observation was noticed EMF low divider resistor has some effect upon the magnitude of VDS leakage. Obviously the concern is for any static phase voltage >12v being present and more of a human body safety artifact to consider.

1. Has TI ever consider how the resistor divider values raises R1/R2 potentiometer drop across the phase drive output to an unsafe level?

Oddly in our test inverter connected launchXL-x49c reducing R2 top value (470k) to 100k reduced 10v VDS leakage <3v well below 40 VDS.

2. How can the drv8320rs or it's master controller have any affect to reduce the 40v VDS leakage across the NexFETS?

A. Is there an internal register control (drv8320rs) that might lead to excessive IDss driving higher VDS in the NexFETS?

Phase A/B input drive/s held low by MCU during idle time and or high impedance state made no difference to reduce 40 VDS.  

Seemingly it is not safe to say since all phases have same leakage they can do no harm. A sweaty repair person might get an unexpected experience should they encounter such leakage. Lets think of the men/women on the front line doing repair jobs perhaps in high summer Tx heat nearing 105°F. Not so much a concern at this early stage of DC motor drives but over time may become more relevant.  

3. How does 9k in the R2 (lower EMF divider position) help to reduce VDS leakage across the phase output circuit to much safer level than 40v? 

4. Might the PGA amplifiers (F280049c) provide a solution to reduce voltage divider circuit values as to shunt IDss off NexFETS and reduce VDS leakage <40v? 

5. Could the drv8320rs Enable pin have some effect on the NexFET idle VDS leakage and or does drv8320rs gate drive controls account for excessive high side VDS?

  • GL,

    This phenomenon is common for this style of driver. There is inherently a small leakage path (100-300uA) from VCP through the high side pull-up FET and out to the gate of the external high side FET. The internal pull down FET is on to make sure that the Vgs of the external high side FET is 0V so this leakage voltage appears on both gate and source of the external high side FET:

    Typically this voltage is only seen if the charge pump is powered and the external low side FET is not switching. You can either disable the DRV, disable the charge pump, or for the external low side FET to be OFF in order to remove this leakage.

    Regards,

    -Adam

  • Adam Sidelsky said:
    or for the external low side FET to be OFF in order to remove this leakage.

    All 3 low drives were off (MCU commanded low) into drv8320rs and NexFET drives test points were low. There must be another path somehow.

  • GL,

    My apologies, I meant to say "force the LS to be ON", this would dissipate the small leakage which happens when the VCP is up but all the output FETs are OFF.

    Regards,

    -Adam

  • Adam Sidelsky said:
    I meant to say "force the LS to be ON",

    Oddly SW forces 3 PWM-B drives On state already for SDK (FOC). That was my first forum question why and there was no real answer why B was forced on. Typically this force of B drives is done as to pre-charge Cboot caps, they float until charged. The drv8320 is not getting the message below.

            // setup the Action-qualifier Continuous Software Force Register
            // (AQCSFRC)
            EPWM_setActionQualifierContSWForceAction(EPWMn_BASE,
                                                     EPWM_AQ_OUTPUT_B,
                                                     EPWM_AQ_SW_OUTPUT_HIGH);

    I noticed the cutoff point of leakage is 40vdc and 48vdc power supply NexFET drives go high starting from 40v. 

     

  • Yea the dead band drops PWM-B the way the SDK(FOC) was configured static dead band, drv8320rs dead band enabled too. I think that is a bad idea to have both dead bad delays x49c and drv8320rs but forum guru say naa not a problem they both on together. So x49c dead band defeats turn on B drives, do not have pass through ability.

    The timing RED/FED edges x49c ePWM module into drv8320 may lead to random issues depending on edge conditions? Perhaps SDK should configure independent RED/FED controls or disable drv8320 dead band.