This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8889-Q1: Device Behavior

Part Number: DRV8889-Q1

Hello,

  1. Does DRV8889-Q1 have an automatic shoot-through prevention function in its each H-bridge? Or, does a dead time control have to be implemented in MCU in its control scheme?
  2. How will the DRV8889-Q1 behave when its output current doesn't reach its current regulation set point due to large load resistance, for example?
  3. Can the DRV8889-Q1 start with any phase when it's turned on?
  4. Does the DRV8889-Q1 require any sequence for external voltages including power supplies to be applied to its pins?
    • I'm worried if some sequence would cause abnormal behavior or irregular current flow due to internal protection diodes, etc.

Best regards,
Shinichi Yokota

  • Yokota-san,

    1. DRV8889-Q1 has integrated FETs. The dead time control will prevent a internal shoot- through in each half bridge. If customers creates shoot through externally, the OCP function will try to protect the device.

    2.DRV8889-Q1 allows 100% duty cycle operating when its output current doesn't reach its current regulation set point due to large load resistance.

    3. If DRV8889-Q1 is not in sleep mode, the Indexer is operating. You can send step signal to start the phase you like.

    4. I don't see a requirement for a sequencer. But, before nSLEEP pin is pulled high, VM input voltage should be stable. After nSLEEP pin is pulled high at VM>UVLO, please give 0.9ms wake-up time, and then, send signals to DRV8889-Q1. nSLEEP pull-up source cannot use DRV8889-Q1's DVDD.

  • Yokota-san,

    1. DRV8889-Q1 has integrated FETs. The dead time control will prevent a internal shoot- through in each half bridge. If customers creates shoot through externally, the OCP function will try to protect the device.

    2.DRV8889-Q1 allows 100% duty cycle operating when its output current doesn't reach its current regulation set point due to large load resistance.

    3. If DRV8889-Q1 is not in sleep mode, the Indexer is operating. You can send step signal to start the phase you like.

    4. I don't see a requirement for a sequencer. But, before nSLEEP pin is pulled high, VM input voltage should be stable. After nSLEEP pin is pulled high at VM>UVLO, please give 0.9ms wake-up time, and then, send signals to DRV8889-Q1. nSLEEP pull-up source cannot use DRV8889-Q1's DVDD.

  • Wang-san,

    Wang5577 said:

    1. DRV8889-Q1 has integrated FETs. The dead time control will prevent a internal shoot- through in each half bridge. If customers creates shoot through externally, the OCP function will try to protect the device.

    Does it mean the dead time control is implemented in the DRV8889-Q1 or not? I found no description in its data sheet.

    Best regards,
    Shinichi Yokota

  • Yokota-san,

    The integrated FET's gate charge is in a narrow range and the dead time prevents the shoot through in the DRV8889-Q1.

  • Wang-san,

    Wang5577 said:
    The integrated FET's gate charge is in a narrow range and the dead time prevents the shoot through in the DRV8889-Q1.

    I understand that the dead time control is implemented in the DRV8889-Q1 and users don't need to care about it externally. Please let me know if I'm wrong.

    Wang5577 said:
    4. I don't see a requirement for a sequencer. But, before nSLEEP pin is pulled high, VM input voltage should be stable. After nSLEEP pin is pulled high at VM>UVLO, please give 0.9ms wake-up time, and then, send signals to DRV8889-Q1. nSLEEP pull-up source cannot use DRV8889-Q1's DVDD.

    What if VM < UVLO when nSLEEP pin is pulled HIgh? How will the DRV8889-Q1 behave?

    Additional questions

    1. Can the DRV8889-Q1 move the indexer several steps at a time while the H-bridges are enabled? In other words, can the DRV8889-Q1's indexer jump to any state while the H-bridged are on? Non-circular 1/2-step is considered, so I'm referring to Table 5 of the data sheet.
    2. In the section 7.3.11.4, the data sheet says, "If the motor is held at a position corresponding to 0°, 90°, 180° or 270° electrical angles, for more than the open load detection time, open load fault will be flagged, as one of the coil current is zero." Does it indicate the DRV8889-Q1 can falsely detect an OL condition at these electrical angles even if it operates normally? If it's correct, how can the false detection be avoided?
    3. How should I understand the parameter tOL, open load detection time? When the DRV8889-Q1 moves a step with a period of less than tOL, 30 ms (< 200 ms (Max)), for example, will it never detect an OL condition?

    Best regards,
    Shinichi Yokota

  • Yokota-san.

    Yes. The dead time control is implemented in the DRV8889-Q1 and users don't need to care about it externally. Please let me know if I'm wrong.

    if VM < UVLO when nSLEEP pin is pulled HIgh, the IC may work and also may not work.

    The indexer has to move step by step. It cannot skip few steps.

    DRV8889-Q1 will report an OL condition if the motor is held at a position corresponding to 0°, 90°, 180° or 270° electrical angles. To avoid the OL fault in this condition:

    a. When the motor stops, don't hold on 0°, 90°, 180° or 270° electrical angles.

    b. when the motor is spinning, make 0°, 90°, 180° or 270° electrical angles' micro-step time shorter than tOL.

    When the DRV8889-Q1 moves a step with a period of less than tOL, 30 ms (< 200 ms (Max)), OL can still be triggered if the load is opened. For example, the output current is zero if the load is opened which is lower than Itrip in most of micro-steps. One step time is shorter than 30ms, but several steps can be longer than 30ms.

  • Wang-san,

    Wang5577 said:
    if VM < UVLO when nSLEEP pin is pulled HIgh, the IC may work and also may not work.

    I guess the DRV8889-Q1 would stay in an UVLO condition after nSLEEP pin is pulled High while VM < UVLO. Is it correct? The DRV8889-Q1 would move to Operating/Disabled mode if VM > UVLO, otherwise, it would go to UVLO if VM < UVLO, I suspect.

    Please confirm.

    Best regards,
    Shinichi Yokota