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DRV8303: reset function

Prodigy 70 points

Replies: 7

Views: 74

Part Number: DRV8303

in data sheet :If RESET is high while ENABLE is inactive, then the registers read as 1.

but if enable is active during reset , what will happen in all registers including fault register?

  • Hi Gehad,

    Thank you for posting to the MD forum!

    Let me take a look at this with our EVM and I'll get a response back to you soon.


    Regards,

    Aaron Barrera

  • In reply to Aaron Barrera:

    Hi Gehad,

    I will be getting to this test this week and provide you a response by the end of this week. 

    Regards,

    Aaron Barrera

  • In reply to Aaron Barrera:

    Hi Gehad,

    When you mention "reset", are you talking about the RESET_GATE bit in SPI?

    If RESET_GATE is asserted while ENABLE is active, it will clear any latched faults in the status registers. This is typically how you would clear any faults in the status registers (or by setting ENABLE low for less than 10us).

    Regards,

    Aaron Barrera

  • In reply to Aaron Barrera:

    Hi Aaron , 

    thanks for your response 
    i mean by reset  : the reset pin 

    datasheet mention one of reset ways: When the RESET pin is high while ENABLE is active.

    what happen for registers values?

  • In reply to Gehad Elkot:

    HI Gehad,

    The DRV8303 doesn't have a RESET pin. Are you talking about the DRV8308? 

    Regards,

    Aaron Barrera

  • In reply to Aaron Barrera:

    yes, i mean 8308 sorry for this error

  • In reply to Gehad Elkot:

    Hi Gehad,

    No worries. When ENABLE is high and RESET is high for longer than 10-us, all registers are reloaded with the values that are contained in OTP memory. All of the faults will be cleared back to 0 and internal states will be initialized. 

    Regards,

    Aaron Barrera

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