DRV8323: sense OCP configuration block diagram and sense resistor usage
Part Number: DRV8323
I have some voltages anomalies at the current sense outputs of my design. I'm using the measurement over the rds_on (SH_x, SNx).
At higher currents the output goes to "0" (=3V) for 5µs, afterwards the signal ist back as expected. The phase current doesn't have these spikes, so the driver seem to work.
Spikes start at ~80A phase current.
Green is the voltage on SOB,
Red is the current measured with clamp meter.
The DIS_SEN =1b, so the fault is ignored. Is there another protection of the SOA output? Or can you explain what happen in these 5µs?
Is it possible for you to try a slightly smaller sense resistor?
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In reply to Adam Sidelsky:
As I mentioned I'm using the rds_on of the low side mosfets for current measurement (2 parallel => rds_on 0.5mR) and I can't change to a sense resistor, because of the PCB space.
Do you have an explanation for these "spikes", is this a known issue with the rds_on measurement?
In reply to Martin Fuchs7:
Are there any updates on this issue?
It's hard to say exactly what is causing the spikes but I can tell you that using the FET RDSON for current sensing is not usually recommended. The RDSON from one FET to the next can change quite a bit and the RDSON also varies with temperature.
Have you checked if you are violating the input max or min for the CSA input?
The problems with the RDSON are known and compensated in via software. I didn't find any information, that RDSON measurement isn't recommended with the DRV8323 Driver.
I checked the CSA input voltages and they are within the spec values.
Did this issue get resolved? Sorry for the delay here.
For me it's no really resolved. I still have no answer to the questions:
"... Is there another protection of the SOA output? Or can you explain what happen in these 5µs?"
Have you checked the status of the VREF/VM supplies at the time of the 5us dip? Are you using the SPI or hardware version of the device?
I'm using the SPI device. The VREF/VM are ok, the phase current is still flowing during the dip.
By the way: on the revision history of the index *c* data sheet is no information, that the mechanical data has changed.
Are you reading or writing any SPI signals when the dip is seen?
What about the CAL pin during the dip?
Can you share your schematic?
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