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DRV8350: tDrive function

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Replies: 6

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Part Number: DRV8350

Hi all

Would you mind if we ask DRV8350?

There is the description on the datasheet P13 as follows;
tDrive is Peak current gate drive time

There is the description on the datasheet P36 as follows;
After the MOSFET turnon or turnoff, the gate driver switches to a smaller hold I HOLD current to improve the gate driver efficiency.

<Question>
tDrive setting : 4000ns
For example, if the gate turns on(or turn off) with in 2000ns, does the gate driver switch to a smaller hold IHOLD current?
What we would like to know is ;
After gate turns on or off, the gate driver doesn't keep peak current in despite of tDrive remaining.
Is our recognition correct? 

Kind regards,

Hirotaka Matsumoto

  • Hi Hirotaka,

    I'm checking on this with the team, I'll get back to you tomorrow.

    Regards,

    Paul

  • In reply to Paul Parrot:

    Hey Hirotaka,

    Assuming no gate drive faults occurs, the I_hold state should be applied only after tDrive expires. So in the example you provided, the gate driver will switch to I_hold only after the full 4000ns tDrive period.

    Regards,

    Paul

  • In reply to Paul Parrot:

    Paul san

    Thank you for your reply!

    the gate driver will switch to I_hold only after the full 4000ns tDrive period.
    ->We would like to confirm one point.
       Could you refer to the attachment file?
    202009217_DRV8350H.pdf

    In case of PWM=80kHz with ONduty=50%, On time is 6.25us.
    In this case, on the Figure33, it might be enough time for IGHx to drive.
    However, if 4000ns tDrive period is fixed time, it seems that there is no enough time for IGLx to drive.
    On the other hand,  if 4000ns tDrive period is fixed time, IGL drive time will be within 2.15us(ONduty:6.25us - IGHx's tDrive:4us -Dead time:100ns).
    When the PWM value is more than 80kHz, this condition will be worse.
    Is our recognition correct? Could you give me advice?

    Kind regards,

    Hirotaka Matsumoto

  • In reply to Hirotaka Matsumoto:

    Hirotaka san,

    As the TDRIVE state machine shows, each gate during their respective on/off phase will be driven at IDRIVE for a fixed TDRIVE time. In reality, the gate will most likely charge/discharge faster than TDRIVE. However the gate will only switch to IHOLD after TDRIVE has expired.

    In the example you provided, the device will check after time TDRIVE if the high side gate has been completely turned off. If so, it may disregard the TDEAD time and start turning on the low side gate a bit earlier. However even in this case, a 4us TDRIVE at 80 Khz with a 50% duty cycle will take up a large portion of your 6.25us on-time. You could try with this configuration and send me some waveforms to review.

    Also it looks like you're using the DRV8350H which fixes TDRIVE to 4000ns. Another suggestion would be to use the SPI version of this device, DRV8350S. With the SPI device you can configure TDRIVE to be 4000, 2000, 1000, or 500ns. The lower TDRIVE times could be better suited to the high PWM frequency you're running in this case.

    Please let me know if you have any questions!

    Thanks,
    Paul

  • In reply to Paul Parrot:

    Paul san

    Thank you so much for your reply!

    We would like to confirm some contents which the attachment file shows finally. 
    20200918_DRV8350H.pdf
    Could you refer to the attachment file?

    Kind regards,

    Hirotaka Matsumoto

  • In reply to Hirotaka Matsumoto:

    Hirotaka san,

    Yes, in the example you provided, switching both gates at the same time with a 4.1us on-time and 4us TDRIVE could result in VGLx not turning on at all, or turning on only for a fraction of the expected on-time. In this case, your two options are to vary the timing between INHx and INLx or use the DRV8350S to reduce the TDRIVE time to something more compatible with your PWM frequency and duty cycle.

    Regards,

    Paul