Hi teams
I am not very clear about the overcurrent protection cycle-by-cycle mode retry operation.
Datasheet mentions that "a new rising edge on the PWM inputs will clear an existing overcurrent fault",
for example if IC detect low side VDS in Ach (VDS_LA), does it means only the rising edge on INLA will clear the fault,
or any rising edge on 6 PWM inputs (INHx and INLx) can clear the fault.
Will the trigger be affected by OCP_ACT setting?
And since this IC has 6x PWM input mode, 3x PWM input mode, 1x PWM mode and independent mode,
each pins function become different in different mode, I am confused about how CBC works under different mode.
hope can get a clear answer from you.
best regards