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Part Number: DRV8353
I am not very clear about the overcurrent protection cycle-by-cycle mode retry operation.
Datasheet mentions that "a new rising edge on the PWM inputs will clear an existing overcurrent fault",
for example if IC detect low side VDS in Ach (VDS_LA), does it means only the rising edge on INLA will clear the fault,
or any rising edge on 6 PWM inputs (INHx and INLx) can clear the fault.
Will the trigger be affected by OCP_ACT setting?
And since this IC has 6x PWM input mode, 3x PWM input mode, 1x PWM mode and independent mode,
each pins function become different in different mode, I am confused about how CBC works under different mode.
hope can get a clear answer from you.
My answer assumes you are using the SPI part, and the cycle-by-cycle bit in the Gate Drive LS register is set to the default (1b). CBC is only used when OCP_MODE = 01b ("VDS Automatic Retry") in the OCP Control register. Regardless of which FET reported a VDS fault, any PWM edge (rising or falling) will clear the fault in this mode.
OCP_ACT = 0b (default) will shut down the half-bridge (high and low side) on only the phase that reported a VDS fault (on either high or low side.) This is the case for every PWM_MODE setting.
As an example, in 3x PWM mode with OCP_ACT = 0b, a fault flag on VDS_HA will shut down phase A's half bridge, but could be cleared by a change in INHB. This is only if CBC = 1b and OCP_MODE = 01b as mentioned before. The same would happen in other PWM modes since any change on an input pin will clear the fault in "VDS Automatic Retry" mode.
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In reply to Omar Naamani:
Thank you for your quick response.
I think it makes me clear.
So in VDS automatic retry mode or Vsense automatic retry mode, any change on any of the 6 input pins (rising or falling edge) will clear the fault.
Since the falling edge can also clear the fault is not descripted in the datasheet, so I would like confirm it with you again.
In reply to user4347805:
No problem. For the DRV8353, either edge on any phase should trigger the CBC reset. However, I am going to run an experiment at the beginning of next week to test this behavior on an actual device. I should be able to confirm this fully by Wednesday October 7th at the latest.
I ran a test to confirm that the falling edge does indeed trigger a CBC reset. The datasheet may only mention the rising edge because VDS monitors are disabled when the associated gate is off, therefore a falling edge would disable fault detection and the CBC reset will immediately clear the fault.
Thank you for the support
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