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Part Number: DRV8353
For the VDS or VSENSE over-current protection of DRV8353, the customer chooses the CBC mode. Is it necessary to have the rising edge of INH or INL of the phase where the over-current is detected when recovering? Or for all 6 inputs, as long as there is a rising edge, it will be reset and the output can be restored?
In addition, will this be related to the setting of OCP_ACT?
If he uses 1x PMW mode, is it to restore output through INHA? Will it affect the Hall signal input number?
No, this is not necessary. If the CBC bit is set, any PWM change (rising or falling) can clear the VDS fault regardless which FET triggered it. if the OCP_ACT bit is set to 0, the only difference will be that only the half-bridge where the fault was present (high or low side) will be shut down.
For example, in 3x PWM mode and OCP_ACT = 0, VDS-HA fault will shut down the A channel and can recover by INHB changing (assuming CBC = 1 and VDS_MODE = RETRY.)
Also note that this CBC bit only effects the operation of the part when the part is in retry mode. In addition to CBC resets, the part will also try to clear the fault after every t_retry period in this mode. Lastly, this info applies in every PWM mode. Hope that helps clear things up! Please let me know if you have any more questions.
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