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Part Number: DRV8353
A customer of mine has a question regarding the control behaviour of DRV8353S in the 6x PWM mode.
In the datasheet the TDRIVE state machine is shown as it puts in a dead time (consisting of the time until Vgs has passed a certain threshold plus the fixated dead time.) This however is only descried for when VINHx and VINLx are toggled at the same time.
This leads me to the following questions:
Thanks for posting on the motor drive forums!
Will the dead time also be added if both signals are toggled with some offset?
The short answer is, it depends. In most realistic cases, yes.
The longer answer is the Smart Gate Drive architecture only needs to insert dead time when transitioning between 0b01 and 0b10. 0b00 to 0b01, or 0b11 to 0b10 does not need to insert dead time as it will pass the handshake criteria.
So I assume you're asking for a criteria where 0b01 -> ends up as 0b00 or 0b11 as a short offset time --> 0b10. In this case, the state machine transitions into the TDRIVE part of the state machine where a gate voltage is falling for TDRIVE. So, if the 0b10 command is received during the TDRIVE part of state machine then it the handshaking criteria (i.e. VGS monitoring) will kick in and it will know to insert dead time.
This means, if the offset between the signals is >TDRIVE, then it won't try to insert the dead time. This is okay, as a Gate Drive Fault will be triggered if the FET is not fully off by the time TDRIVE has completed. Otherwise, the FET will be off and there is no risk of shoot through.
How much can the fixated dead times jitter?
I will acknowledge that the dead time specifications in the datasheet do not list a min or max, which would answer your question. As such, my recommendations are not in the datasheet, and therefore, do not hold the same legal weight as putting the numbers in the datasheet.
The values listed will not deviate on the left side (or faster than the selected dead time) by more than 5%. However, the dead time can vary on the right side (or longer than the selected dead time) by 100% of the selected value when switching from high side to low side.
Hopefully this design makes sense as we want to guarantee the minimum dead time and then the extra delay "is introduced due to the need to discharge the voltage present on the internal VGS detection circuit". This is in the "TDRIVE: MOSFET Gate Drive Control" section of the datasheet can you can read more there.
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