Part Number: DRV8889-Q1
1. We have 8 motors, 1 to 4 of which is SPI in series for control, and 5 to 8 of which is another SPI for control. /Is there any precautions for this application?
2.DRV8889's 18Pin:Step, 19Pin:DIR, 20Pin:DRVOFF are suspended. All three functions are controlled by the CTRL3 register./Is the application appropriate?
3.EMI design: The capacitance between each phase output by DRV8889 two phases is 10nF, and a 10nF capacitor is pulled to the ground below each phase./Are there any other points to be noted in addition to the tuning rate for EMI design?
4.Layout: Are there any matters needing attention?
#1 and #2 are somewhat related - with the daisy-chain configuration, and stepping through SPI, the step rate will be somewhat lower than what can be achieved using the dedicated STEP input pin. What is your SPI clock and maximum desired stepping frequency? Otherwise the daisy-chain you have will be fine.
For #3, we have a blog post that talks about EMI and this device. The device has EMI counter-measures built-in. The internal oscillator and charge pump employ spread spectrum clocking (always active), and the slew rate is adjustable. https://e2e.ti.com/blogs_/b/analogwire/archive/2019/11/19/how-stepper-motors-improve-noise-and-efficiency-in-automotive-system-design
In the schematic I didn't see any local bulk capacitance on VM or supply filtering - is that on another page?
#4: From what I can tell in the attached picture, it looks like you captured the layout recommendations in the datasheet. Did you have any specific concerns?
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In reply to Michael Erdahl:
Any further questions or can I close this out?
Ok,close this case,thanks!
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