Hi Experts,
Customer wants to know the behavior when CP1 pin and CP2 pin is open. When PVDD1 is 28.2V or higher, GVDD voltage begins to decrease then nFAULT pin is asserted. Is this expected behavior?
Customer is usually use DRV8302 with PVDD = 24V. In order to detect the soldering failure of CP1 pin and CP2, if this behavior is expected, they want to add the test condition like that applying 30V at PVDD and see if nFAULT pin is asserted or not.
Regards,
Uchikoshi