DRV8353: Strange gate driver waveform

Part Number: DRV8353
Other Parts Discussed in Thread: TMS320F28375D, , CSD19536KTT

Hi guys,

I'm working on an +48V battery powertrain project.

I'm using TMS320F28375D MCU and DRV8353SRTAR mosfet driver.

The application work in a custom PCB. This is part of the schematics (I can't attach all due to "confidential" issue). The D1201 is NOT mounted.

So, I made some calculations with my MOSFET's values using slva714d. I think these maybe correct:

The DRV8353 is set accordly with the calculation attached.

Now, the problem regards the waveform of the High side gate MOS. The deadtime is generated inside the MCU (~1200ns at the moment...I'm tuning the driver and so I go with caution...). I also use the default deadtime of the DRV8353 (I don't disable it).

This is the waveform regard T1201 and T1202.

You can see the strange behavior in the falling edge of the High side mosfets.
I tried to reduce PWM freq and change source/sink Idrive without success. Where is the error? Any suggest?

Best regards,

  • Hello ,

    I'm assuming these waveforms are V_gate to GND, can you measure them while also measuring VCP and V_SHx and assign a Math channel down that subtracts V_GHx - V_SHx?

    The V_GLx from high to low transition looks pretty normal (besides the fact the dead time is pretty long, as you've stated) but the V_GHx high to low transition does sit a bit higher than expected. The anomaly lasts around the duration of the dead time shown during the V_GLx high to low transition. As we short the high side gate voltage to the high side source (or phase voltage) we expect them to end up at the same voltage to turn off the gate. So if you measure V_GHx -V_SHx and they are the same, then the gate driver is doing its job to make sure V_GS < V_th to turn off the FET and the voltage on the source is high until the LS FET pulls the energy out to GND.

    Monitoring VCP is just to check to make sure VCP isn't browning out during this time so it remains stable during this time then there won't seem to be any problem with the high side voltage supply.



  • Hi Cole,

    thx for your time.

    I tried to made the Vgs measure.

    Can you suggest me a better setup for IDRIVE current? I think the rise time of the High Side gate voltage need to be more fast.

    Remain a little ringing when the mosfet turn off. Can you provide some suggest?

    Thx in advance,


  • Hello Stefano,

    Looks like the motor driver is doing its job and collapsing V_G and V_S together to make sure the FET is turned off. 

    So, this is essentially dead time. As the FET turns off, the node becomes "high impedance". The motor and parasitic inductance hate that the change in current (V = L*di/dt where di/dt is negative or decaying) and a Back EMF voltage is generated that pushes up above the VDRAIN voltage to ensure current keeps flowing in the same direction. The body diode of the FET experiences the reverse recovers and we complete transition to the low side turning on, to pull the high side source to GND.  No issues here, textbook MOSFET behavior.

    To your point, the ringing is a bit concerning. As you've correctly asked, IDRIVE is the next step to reduce this outside changing or adding any components to the design. 

    I'm writing an app note on this, and I'm going to ask for you to read this and see if you can use the example

    Example IDRIVE Calculation

    For this example, we’ll take the DRV835x family of devices paired with the CSD19536KTT power MOSFETs, which are showcased on the 54-V, 1.5 kW, >99% Efficient, 70x69 mm2 power stage reference design for 3-phase BLDC motors: TIDA-010056.

    The steps for calculating gate current that should be used are:

    1. Find your FET part number and associated datasheet.
    2. Locate the Qgd value in the datasheet. The typical Qgd is acceptable but always be aware of the min/max/tolerance of the Qgd.
    3. Estimate needed VDS rise and fall time. For many customers between 100ns to 300ns are acceptable as a rule of thumb



    ( 2 )


    • I_DRIVE = The current sourced to or sunk out of the gate
    • t_RiseFall = The equivalent rise or fall time for the VDS
    • Q_GD = The inherent gate to drain charge for the MOSFET


    For the case of the CSD19536KTT, QGD = 17 nC and we can use the rule of thumb to put 100ns into the rise and fall.


    ( 3 )


    ( 4 )

    The DRV835x family has options for 150mA or 100mA source and 100mA sink. Source refers to the current taken from the gate voltage supply and pushed into the FET, which corresponds with the rise time; and sink refers to the rate at which charge is pulled from the gate of the FET and pushed to the source of the FET, which corresponds with the fall time.

    Remember, we are merely using a starting gate drive current that was calculated with a safe rule of thumb. This is a first order equation and will not exactly match what is seen in the real system, but the goal is to get within a reasonable starting point. This is why we round down if the device does not have an exact selection, to make the equivalent rise or fall time to be longer than the calculated value. We expect designers to increase or decrease this number after testing.



  • Hi Cole,

    regard the same question I sended you last week. Now I'm testing the firmware in the "real" hardware but I have a strange behaviour in MOSFET switching. I'm using DRV8353 and SQJQ410EL-T1_GE3 nMOS. From datasheet i found Qg = 20nC so I set Idrive to 150mA (source) and 200mA (sink).

    For EPWM configuration I used this code for all the EPWM:

    void setupEPWMActiveHighComplementary(uint32_t base)
        // Use EPWMA as the input for both RED and FED
        EPWM_setRisingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);
        EPWM_setFallingEdgeDeadBandDelayInput(base, EPWM_DB_INPUT_EPWMA);

        // Set the RED and FED values
        EPWM_setFallingEdgeDelayCount(base, 35);
        EPWM_setRisingEdgeDelayCount(base, 35);

        // Invert only the Falling Edge delayed output (AHC)
        EPWM_setDeadBandDelayPolarity(base, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);
        EPWM_setDeadBandDelayPolarity(base, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);

        // Use the delayed signals instead of the original signals
        EPWM_setDeadBandDelayMode(base, EPWM_DB_RED, true);
        EPWM_setDeadBandDelayMode(base, EPWM_DB_FED, true);

        // DO NOT Switch Output A with Output B
        EPWM_setDeadBandOutputSwapMode(base, EPWM_DB_OUTPUT_A, false);
        EPWM_setDeadBandOutputSwapMode(base, EPWM_DB_OUTPUT_B, false);

    If the motor running, in many cases I have this acceptable situation:

    ...but sometime this is the behaviur:

    How you can see, I have large ring during switching (~65MHz freq.). This ring goes to ground plane and create many problems in other signals.
    Please, any advice for me?
    I try to change deadtime (in FW), change deadtime (in DRV8353), change Idrive values...but this issue still remain.

  • Hello Stefano,

    Please note that Friday 4/2 is a holiday in the US. The team will get back to you on Monday.



  • Ok, Matt.

    Waiting for Monday, I made other tests and the ringing still remain.

    In this pic you can see HS MOS Vgs. A very noisy ring appear when LS MOS turn ON.

    Deadband now is configured as 400ns (DRV8353) and Idrive to 150mA (source) and 200mA (sink).

    Best regards,

  • Hi Stefano,

    In the meantime, I do have an article which discusses the source of MOSFET ringing due to parasitic elements on the PCB: www.allaboutcircuits.com/.../

    Low-side MOSFET turn ON ringing can be caused by a few things: parasitic inductance of the sense resistor, parasitic inductance of the ground return path, parasitic inductance between the high-side and low-side MOSFETs, or body diode reverse recovery.

    In your case it looks like current is flowing into the phase node, and the fall time of SHx is controlled by the IDRIVEP of the low-side MOSFET.



  • Hello Stefano,

    I completely agree with Matt. PCB parasitics are a main reason why we see the ringing. But I'll talk more on that later.

    Comments about the waveforms:

    The interesting note is that it looks like we are seeing this infrequently which means the motor current is in a state where Back EMF will be generated and influence the severity of this ringing behavior. To quote Matt "In your case it looks like current is flowing into the phase node, and the fall time of SHx is controlled by the IDRIVEP of the low-side MOSFET"

    I'm sure if we zoomed into the falling edges of "good" behavior vs. "ringing" behavior and displayed on the other phase voltages, we should see differences in the timing of the waveforms and the voltage levels on other phases.

    That being said, I don't think we need to do that. We should look into suppressing or mitigating the ringing when it does occur.

    Comments on IDRIVE and Dead time:

    I want to be clear that IDRIVE and dead time will change the behavior of the ringing. As long as there is an L and a di/dt, we will get voltage spiking (V = L* di/dt). Dead time and IDRIVE both influence the di/dt part of the equation where L remains constant . So, if you were to compare waveforms of the ringing of high IDRIVE and longer dead time, with low IDRIVE and short dead time, I'm sure you'll see a difference in the spikes of the voltage that is generated.

    With that being said, we can't change L, because you've already made the layout, so we do not expect to see the voltage spiking to disappear. Let me reiterate, from what I can tell, there are no mitigation or suppression circuits on your board that will reduce the inevitable, voltage spiking.

    Suppression and mitigation circuits:

    Go look at Matt's article (he wrote it: https://www.allaboutcircuits.com/industry-articles/understanding-and-mitigating-motor-driver-board-parasitics-through-simulation/ ), its the exact behavior you're seeing on your waveforms. If you compare your schematic with the circuits he uses, I'm sure you'll have some, but not all of them. You might want to consider a redesign to add these circuits.

    Other Suppression and mitigation techniques:

    Good layout techniques reduce the L in the equation. Luckily we have a app note for that too: http://www.ti.com/lit/an/slva959a/slva959a.pdf

    I suggest you read it. Here's some extra tips for getting the layout right in context of the DRV835x family. Compare the app note and advice with your layout, you might want to do a redesign if you didn't consider all of this advice:

    • The real PCBA has parasitic components that get added to the schematic, in addition to the components
    • Long traces add capacitance and resistance.
    • Thin traces also add resistance and inductance.
    • 10mil/Amp is a minimum rule of thumb for the minimum trace width but it also applies to vias, specifically angular ring area. The larger or wider the traces and vias are, the less inductance.
      • As such, gate current source and sink paths should be at least 15mil, 20mil is preferred
    • Making traces thinner and smaller add impedance mismatch.
    • More current means higher voltage spiking.
    • Component footprints add parasitics.
    • Vias in the path add parasitics.
    • The return path must be understood: DC current will spread out on the GND planes as far it can reach where high frequency current gravitate underneath the trace. This is why common GND, as opposed to split GND, is always better unless current will flow near the trace
    • Common ground is always better than split GND. Split GND is only ever used to divert large current or high frequency content away from sensitive components. That means the signal needs to be traveling towards or near those components to warrant a split GND.
    • Be the current, draw the loop from the source of the pin or component to the GND pin or external connector. Make it as small as possible. This means adding lots of vias or rearranging components
    • Our experience says the cost between 100 and 300 GND stitching vias is negligible in PCB manufacturing. Create a plane of GND stitching vias to connect outer and inner layer GNDs.
      • Manually place GND stitching vias where the automated tools fail
    • Order of importance or signals and component locations on an IC are:
      • voltage regulators (like VCP or VGLS),
      • input regulators and referenc voltages (like VM and GND),
      • signal path and higher current paths (like GHx and GLx),
      • digital signals that switch often (like SPI),
      • digital signals that don’t switch often (like nFAULT)



  • Hi Cole, first a big thanks for your useful information. I made much tests (...following your advices). I never wrote about PCB shape. It's a very strange shape, not symmetrical and so, It was not possible to design a "symmetrical" power-bridge. It's a 6layers PCB and the gate drive track are 12mils. However, inserting an 10R Rg on High-Side and an 1R Rg on Low side and tuning Idrive to a bit higher value, now I have a huge improvement also with high load. Still remains a little ring at lower frequency (~5.4MHz) that is not so much different from the one calculated using measurement instruments. With LC meter I had a ~330nH from Vsupply to VDrain and considering MOSFET Coss (~3750pF) i have Fring = 1/ (2 * pi * sqrt(L*C)) = 4.524MHz. I will create a PSpice simulation model to study the best snubber solution for my design. Thx for your time.

  • Hello Stefano,

    Sounds great. I can't remember if the article talking about the calculation process but I'll add a helpful link for calculating the snubber design for those who don't have access to the link: https://e2e.ti.com/blogs_/b/powerhouse/archive/2016/05/05/calculate-an-r-c-snubber-in-seven-steps

    For a clarification, I will acknowledge that real life doesn't allow all of the FETs to be equidistant from each other. As a result, I would just consider it a risk. If you start seeing damage originating on one phase, and its the one that's farthest away, you'll learn that the layout might be contributing to the ringing that results in damage.

    As for the GHx, SHx or GLx and SLx/SPx/SNx traces for a given phase; definitely try to keep those similar length and thickness, even though GHA might be much shorter than GHB, etc.



  • Hi Cole.

    I had made much progress but a issue still remains.
    I'm a bit frustrated about this. I can't remove it!
    At the moment, to remove all other spike and ring voltages, I need to tweak every half-bridge in this manner:
    1) HS driver register is set to 0x311;
    2) LS driver register is set to 0x722;
    3) I added gate resistors. 10R for LS, 22R for HS;
    4) I added 10n Cds caps on the HS mosfets;
    4) I added 6n8 Cgs caps on the HS mosfets;
    Now all working well but I can't remove this ringing.

    Despite I set a high dead-time the ringing is here!

    This is the phase voltage:

    I don't know if this behaviour is due to reverse recovery time, high dv/dt on phase voltage. How I can mitigate this ring?
    Any advice for me?
    Thx a lot for your time.

  • Hello Stefano,

    Can you send your schematic and layout? From what you've described, you haven't done anything wrong from the adding components and adjusting settings. 

    Feel free to send me a private friend request and then you can send the files over private messaging. 


    Also, you've done a good job reducing the ringing, you were almost -20V if I recall, now you're below -10V. I don't think you're violating abs max anymore (listed below)

    Note, ringing is inevitable because of the parasitic, you don't need to make it disappear completely. You'll just need to wait a little bit longer to sample current at the CSA as the ringing settles down. This is very typical. Your goal should be to get ringing below abs max and below any CSA sampling time.

    Here's an example of a ti design: https://www.ti.com/tool/TIDA-010056 54-V, 1.5 kW, >99% Efficient, 70x69 mm2 power stage reference design for 3-phase BLDC drives. They still have ringing in their waveforms if you go into the design (not as much as you, but it still exists.)