DRV8323: SPI communication and PWM output are abnormal

Part Number: DRV8323

Hi Team,

The customer is experiencing the following problems:

1. SPI communication problem: all of them are 0 when reading the register, and the oscilloscope looks at SOMI, there is no waveform

2. PWM drive problem: the gate voltage output by DRV8323 is abnormal. The input to DRV8323 is a 1khz PWM signal

The schematic diagram is as follows:

The gate voltage waveform of the A-phase upper half bridge:

The gate voltage waveform of the A-phase lower half bridge:

Phase A output waveform:

B-phase upper half bridge gate voltage waveform:

B-phase lower half bridge grid voltage waveform:

B-phase output waveform:

Thanks,

Annie

  • Hi Annie,

    Please review this E2E FAQ about SPI communication.

    Does the customer have a pull-up resistor on SDO? It is an open drain output. (nFAULT is also open drain)

    Thanks,

    Matt

  • Hi Matt,

    He did not add external pull-ups. But the internal pull-up is added to the SPI of STM32. If he does not use SPI configuration but directly uses the default mode (is it 6PWM by default?), and drives in the default mode, there is still a problem with the output.

    Thanks,

    Annie

  • Hi Annie,

    Default is 6x PWM mode. 

    What is the value of the internal pullup on SDO in the MCU? I'd recommend a 1k - 10k pullup to DVDD for the SDO pin. 

    Please confirm that the clock phase and polarity are correct to match the SPI communication settings in the datasheet.

    If you read back 0 from the registers, then it is not being written correctly and there is a good chance that the default IDRIVE settings (1A/2A) are causing the gate and phase output issues. 

  • Hi Aaron,

    The MCU has a weak internal pullup. However, even if he does not use the SPI configuration, but uses the default configuration, which is driven by 6*PWM, the result is not normal. Is there a problem with the default configuration?

    Thanks,

    Annie

  • Hi Annie,

    The default configuration for the DRV8323 IDRIVE settings are 1A/2A for the SPI variant. I will need to see the schematics for the MOSFET powerstage to see the Qgd of the MOSFETs used and whether they may be extra components such as gate resistors or gate-drain capacitors. 

    The waveforms showed large transient spikes on the upper half bridge waveforms and lower half bridge waveforms. A good first step to debug would be to lower the IDRIVE setting to the minimum, or a setting that would be best for the customer's application based on this IDRIVE FAQ:
    https://e2e.ti.com/support/motor-drivers/f/motor-drivers-forum/796378/faq-selecting-the-best-idrive-setting-and-why-this-is-essential

    But in order to change the IDRIVE setting, we need to get SPI to work on this device. 

    Can the customer read a SPI register that isn't default 0x0000, such as register 0x03?

    Can you ensure ENABLE = 1?

    Is there a pullup resistor on nFAULT to 3.3V?

  • Hi Aaron,

    first of all , the customer still can't read the registers, all of them are 0. 

    He ensures ENABLE = 1, because the voltage of DVDD is about 3.3V. It is normal.

    The nFAULT pin is also internally pulled up, and the voltage is also 3.3V.

    powerstage, he used NMOS, IRF7480, Qgd with 44nC

    Thanks,

    Annie

  • The customer reduced IDRIVE and the output was normal.

    But there are two problems:

    1. He gave phase A a constant duty cycle, why is the output not constant? 

    2. Phase A and Phase B output are normal compared to before. But phase C is the same as before, it is abnormal. Before, the gate of the upper half bridge of phase C was always about 12V, and the gate of the lower half bridge was a very narrow pulse, and this is also the case now.

    Voltage waveform of the gate of the upper half bridge of phase A:

    The gate voltage of the B-phase upper half bridge (normal):

    C-phase upper half bridge and lower half bridge (abnormal):

    Thanks,

    Annie

  • Hi Annie,

    Because customer reduced IDRIVE via SPI, does that mean he got the SPI settings to work? If so, what was the resolution? 

    Can the customer replace the 4.7 ohm gate resistors with 0-ohm resistors for now? Adding gate resistors complicate reduce the configurable IDRIVE current and should only be used if a gate drive current lower than the minimum settings (10mA/20mA) is needed for better performance. I would recommend IDRIVE settings around 200-400mA source/400-800mA sink based on 44nC Qgd MOSFETs used. 

    Is the customer using 6x PWM mode? Does the motor spin? Are any faults generated? 

    For the screenshots above, it's a little confusing piecing together what's happening at the gate driver level from individual gate waveforms without seeing the behavior of related signals at the same time. Can you provide context when these screenshots were taken (startup, motor spinning, etc.?)

    After replacing the gate resistors with 0-ohms, can you record INHx, GHx-SHx, and SHx-GND in the same scope capture for each phase? This will help with seeing if there are any issues in powerstage design. 

    Thanks,

    Aaron

  • Hi Aaron,

    The customer found that the screen he replied last time had some problems. At that time, he set the 3PWM mode, and then drove in 6PWM mode. Now that it’s revised, it’s still a big problem. 

    At present, SPI should be able to write data (although he can't read it). The figure below is driven in 6pwm mode. There are glitches on the upper half bridge gate voltage waveform. When he lowered the IDrive value, the glitch would be reduced, but the waveform was almost unchanged. As can be seen from the figure below, it should be the problem that the MOS of the lower half bridge is not turned on. But neither the upper half bridge nor the lower half bridge of phase C is opened.

    1. From top to bottom, it is phase A input-the gate of the upper half bridge of A-phase A output

    2. From top to bottom are A phase input-A phase upper half bridge gate-A phase lower half bridge gate

    3. From top to bottom are B phase input-B phase upper half bridge gate-B phase output

    4. From top to bottom, it is B phase input-B phase upper half bridge gate voltage-B phase lower half bridge gate voltage

    5. From top to bottom are C phase input-C phase upper half bridge gate voltage-C phase output

    6.C phase input-C phase upper half bridge gate-C phase lower half bridge gate

    best Regards,

    Annie

  • Hi Annie 

    Our expert will get back to you tomorrow!

    Thanks,

    Matt

  • Hi Annie,

    SPI-related

    Please share SPI code here or offline to debug SPI code to confirm SPI write and reads. Since the gate driver is not outputting correct gate drive waveforms, I would expect nFAULT to go low and gate drive faults to occur. These faults should be able to be read using SPI. 

    Gate-drive related

    Please share current IDRIVE settings used to capture above waveforms. If IDRIVE improves performance as it is lowered, please lower the IDRIVE to reduce gate drive glitches on high side of phase A and see if we get any outputs on phase C.

    I noticed there are 3 different grounds: GND, AGND, and PGND. Are these connected anywhere in the schematic? These split grounds need to ensure that in layout they are connected and that are are no difference in voltage between the ground planes or else FETs may not turn on properly.

    I would like to review the layout for this design. Can you share the layout files over the thread or offline?

    Thanks,

    Aaron