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DRV8912-Q1: DRV8912-Q1 DO Latency

Part Number: DRV8912-Q1

Hi All,
I have to design an FPGA I/F for the DRV8912-Q1 Do driver.
We have a couple of DRV8912-Q1 devices connecting in a daisy chain.
My question is: Can I update the whole 12 DO's simultaneously or the device can have only 8 bits of data per one C.S? meaning there is a built-in latency between groups of 4 DO's