• Resolved

Interfacing Elpida DDR2 with Omap4460


I am trying to interface Elpida DDR2 EDB8164B3PF with OMAP4460, for this do I need to make changes to x-loader src code?

In the file <x-loader_src>/cpu/sdram_elpida.c, some const ddr_register structure are defined:


                     const struct ddr_regs ddr_regs_elpida4G_400_mhz_1cs = {
    .tim1        = 0x10eb0662,
    .tim2        = 0x20370dd2,
    .tim3        = 0x00b1c33f,
    .phy_ctrl_1    = 0x449FF408,
    .ref_ctrl    = 0x00000618,
    .config_init    = 0x80800eb2,
    .config_final    = 0x80801ab2,
    .zq_config    = 0x500b3215,
    .mr1        = 0x83,
    .mr2        = 0x4
};      ......and many more

So from where these values i.e. tim1,tim2,phy_ctrl1,mr1.....etc are calculated?

I have explored the datasheet for the respective part no, but haven't found anything useful. Are these values computed from EMIF specs?

  • Harman,

    If this is the same LPDDR2 part used on Blaze or Blaze Tablet, the structs are already present in sdram_elpida.c.  If not, you will need to modify these values, which are computed from the datasheets.  You can contact your TI representative for access (under NDA) to an application note and spreadsheet that will assist with the calculations.  Note that for basic bootup, as long as the size/geometry parameters are set correctly (namely SDRAM_CONFIG), you should be able to boot and use the board, and you can set the optimal timing parameters later.


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