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TPS1HA08-Q1: LATCH and EN pins to clear faults

Kevin Ginunas
Expert 4485 points
Part Number: TPS1HA08-Q1

Team - question from my customer below:

"We would like to understand how the LATCH Pin works in TPS1HA08B-Q1.

 Actually our idea is to use only two lines from the controller i.e. EN and LATCH to FET.

 We are not preferring auto recovery in case of thermal shutdown fault. So could you please suggest how to use LATCH pin along with EN to clear faults.

 Remaining pins we are planning to Keep permanently in one state."

Thanks,

-Kevin 

  • 0
    TI__Genius 16390 points

    Hi Kevin,

    Customer can pull LATCH pin high and the device will latch off when a fault happens. When customer wants to reset the fault, they can pull LATCH pin low, and after device resumes functioning, they can pull LATCH pin high again.

    The problem of only using LATCH and EN is that customer wouldn't know when a fault happens, and they wouldn't know when to set LATCH pin high and low to reset the fault in this case. It would be suggested for customer to monitor SNS or ST pin to get the device status.

    Please let us know if you have further questions.

    Regards,

    Yichi

  • 0 in reply to Yichi Zhang.
    TI__Expert 4485 points

    Thanks Yichi - few more questions from customer:

    "We are trying to duplicate current operation and fault operation (as monitored by SW) using two pins : OUTPUT_EN (turns output ON) and OUTPUT_FB which monitors voltage at the output.  

    With the present output when a fault occurs the output is latched OFF, the SW detects from feedback signal that the output is not in the proper state and can try to reset the output by cycling the OUTPUT_EN signal (OFF then back ON).

    So for the TI FET, if we tied the EN and LATCH signals together and kept our current analog OUTPUT_FB am I correct that:

    • Output is turned ON by setting OUT_EN and LATCH inputs HIGH.
    • If a fault occurs, the output will be latched OFF
    • External OUTPUT_FB signal would tell µC that the output is not in proper state
    • SW cycles OUT_EN and LATCH from HIGH to LOW and back to HIGH to clear fault latch and try to re-engage load if fault has cleared.  "
  • 0 in reply to Kevin Ginunas
    TI__Genius 16390 points

    That's correct understanding. It should work in this case.

    Regards,

    Yichi