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Original question:

UCC21732-Q1: FLT and RDY Fault

UCC21732-Q1: False FLT latching under very high dI/dtd

Jonathan Moran1
Prodigy 45 points
Part Number: UCC21732-Q1

Hi guys,

I have had great success with this gate drive chip so far driving SiC modules in a high power traction inverter for an electric motorsport application. Due to the specific application we do not design for DESAT/OC nor required to meet any EMI regulation, efficiency is the highest priority in the design.

Reducing our switching time with the latest design has shown great potential, gate ringing and Vds ringing are comparable to the power module manufacturers example waveforms and Vds overshoot significantly less than theirs. The ringing is around 30MHz.

The limiting factor for us now are gate drive IC FLT latches. The OC pin is grounded with a 0R 0603 in parallel with 47pF 0603, however I have also tried lifting pin 2 (OC) from its pad and shorting it to pin 3 (COM) with solder, this still results in a FLT state under medium dI/dT.

Can you think of any other ways I could prevent FLT latch from occurring? I have considered the auto reset connection however I am concerned this will affect the integrity of the gate signal duration under repeated faults

  • 0
    TI__Genius 10652 points

    Jonathan, 

    Could you please sharing a schematic, layout and scope captures of the false FLT tripping: VDS, ID, Gate to start. 

    How is AIN pin connected?

    Jonathan Moran1 said:

    The limiting factor for us now are gate drive IC FLT latches. The pin is grounded with a 0R 0603 in parallel with 47pF 0603, however I have also tried lifting pin 2 (OC) from its pad and shorting it to pin 3 (COM) with solder, this still results in a FLT state under medium dI/dT.

    Grounding FLT pin has no effect on false latching, it is simply an open drain input and wont have any impact. For the purpose of testing false OC triggering / FLT i would ask you to connect it with a pullup which would help us see the timing. 

    FLT could be triggered by excessive noise and certainly by large EMI and therefore di/dt in the system. 

    Best

    Dimitri

  • 0 in reply to dimitri james
    Prodigy 45 points

    HI Dimitri, 

    Many thanks for your input, I am happy to share waveforms and layout via email. The FLT pin is floating and unused, it is the OC pin that I have shorted to SRC.

    AIN is connected to an analog circuit referenced to SRC to measure the voltage over an NTC connected through to SRC. Do you think this could cause EMI disruption?

     Also happy to measure FLT pin to get exposure to fault timing if required

    Cheers,

  • 0 in reply to Jonathan Moran1
    TI__Genius 13470 points

    Hi Jonathan,

    I'll be closing this thread. We can continue our conversation over email starting with the waveforms and layout.

    Best regards,

    Andy Robles