I have had great success with this gate drive chip so far driving SiC modules in a high power traction inverter for an electric motorsport application. Due to the specific application we do not design for DESAT/OC nor required to meet any EMI regulation, efficiency is the highest priority in the design.
Reducing our switching time with the latest design has shown great potential, gate ringing and Vds ringing are comparable to the power module manufacturers example waveforms and Vds overshoot significantly less than theirs. The ringing is around 30MHz.
The limiting factor for us now are gate drive IC FLT latches. The OC pin is grounded with a 0R 0603 in parallel with 47pF 0603, however I have also tried lifting pin 2 (OC) from its pad and shorting it to pin 3 (COM) with solder, this still results in a FLT state under medium dI/dT.
Can you think of any other ways I could prevent FLT latch from occurring? I have considered the auto reset connection however I am concerned this will affect the integrity of the gate signal duration under repeated faults