Figures 65-68 of the datasheet appear to show a delay (approximately 800 us) between the EN pin going high and the start of the ramp on the output (see image below). However, the Soft Start timing characteristics in section 6.6 of the datasheet indicate that the soft-start time starts on the rising edge of the EN pin. Is there an internal delay between the rising edge of the EN pin and the control logic starting to switch the high side FET?