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TPS43000: Information about Type III compensator gains

Part Number: TPS43000
Other Parts Discussed in Thread: TINA-TI

Hello,

I have been using the TPS43000 in a ZETA DC/DC converter with a good results since 2017, using a network experimentally derived from the SEPIC circuit in the data sheet. To be noticed that we use the PFM with DCM, so the regulation should obtain some benefits from this configuration.

Recently, I have dived deeper in the compensator network to optimize as most as possible the behavior against transients increasing the bandwidth; in the data sheet I have found a unit gain bandwidth of 5 MHz and assumed a A0 gain of 1000 for the internal feedback OPAMP.

Now, going to the point, essentially, increasing the bandwidth means to increase the gain but we have met some problem of stability at certain levels of gains: it seems that with gains higher than 20 dB between poles and/or higher than 0 dB between zeroes, the PFM is held also at output current values where it should not, like the output of OPAMP (internal at TPS43000) will be in someway saturated!

Having a look at the reference circuits in the data sheet SLUS489 − OCTOBER 2001, I have noticed that the gains in the compensator networks proposed are really low:

  • the maximum gain between poles is +11 dB for SEPIC topology
  • and between zeroes is -4.5 dB in the BUCK topology. 

 At this point, I do think that should be a limits in the gains due some parameters, I may suppose they are the maximum compensator output voltage (or modulator ramp voltage) and the regulation drift (in PFM is the 2% of Vout). But all those are speculations, then I'd like to know something more to obtain the maximum from the circuit I have designed.

Of course, it might be that everything above is wrong.... then tell me, please!

Thanks a lot for helping me.

Maurizio

  • Hi Maurizio,

    Thank you for considering the TPS43000.  I am afraid there is misunderstanding about the SEPIC loop gain, which is not determined by R3 but by R1.  Also, the compensation depends on topology and also the power circuit design, so they are not expected to be the same.  Please refer to the following article for the proper loop compensation design.

    slup113-Control Loop Cookbook by LDixon.pdf

    Thanks,

    Youhao Xi, Applications Engineering

  • Thanks for reply, Youhao....

    The document is interesting, I know most of the concepts .... but it doesn't help also because the Type III compensator is not covered.

    I know that's what I wrote yesterday about gains is not the exact real situation because in the type III voltage mode compensator, the gain drops at -20 dB/dec from the pole in origin to the 1st zero, it remains flat up to 2nd zero, then it rises at +20 dB/dec up to the 1st pole, again flat up to 2nd pole then drops again at -20 dB/dec, in the asymptotic Bode plot.

    But for the quick evaluation, roughly, the gain between the zeroes is done by R2/R1, while the gain between the 2 poles are done by R2/R3. It is more complex than that... but it helps to understand from where to begin.

    Now, having a plot of my modulator and power filter, I tried to extend the bandwidth around 50 kHz because the ZETA topology doesn't have the RHP (even if there are other issues due the 4th order L-C combinations).

    So, I started to set the gain between zeros at 0 dB (R2 = R1) and to move 2nd zero and 1st pole to have the necessary gain for setting the cross-over frequency around 50 kHz.

    The values I have found, having Rbias =10 kOhm, are: R1 and R2=37.4 kOhm, R3= 1 kOhm, C1=4.7 nF, C2=27 pF, C3=680 pF.

    With those values the circuit is stable wit Vin from 3 to 4.25 V, both in PFM and CCM but if I change C3 to 1 nF, the circuit works ever in PFM, never in CCM, and the overall efficiency is very low.

    I understand that you cannot be extremely accurate but I hope you can drive me in the right direction.

    Thanks

    Maurizio

    PS: the document at the link is not complete, it lacks of all annexes ....

  • Hi Maurizio,

    Type III is based on Type II by adding another pole and zero at the high side resistor of the feedback divider, to help stabilize the voltage mode controlled converter loop. You have the freedom to place the pole and zeros in accordance to the power plant characteristics. Below is another article by TI engineer in which covers the Type III compensator applications.  Hope this can help.

    https://www.ti.com/lit/pdf/slva633?keyMatch=LOOP%20COMPENSATION&tisearch=search-everything

    Thanks,

    Youhao

  • Thanks again Youhao.

    Indeed, I know that literature slva633... I have used it to try to understand the overall behavior because the ZETA converter is "close" to a flyback type without RHP zero and with the PWM module connected in a different way.

    In any case, having such documents studied, I am still wondering about of a few things, at least:

    1. the parameters for TPS43000 are still unknown, I have only the unit gain bandwidth, 5 MHz but nothing about its A0 gain and the amplitude of the ramp Vp
    2. about the model PWMVM, in the schematic the CCM-DCM symbol has 5 terminals (s d a k ctrl) but in the TINA-TI model PWMVM given in the appendix, only 4 terminals are listed and with different names (a c p d) which seems to the Vorpérian PWM switch(???).
    3. in the TINA-TI I cannot found that CCM-DCM symbol: where is it?

    Again, while I thank you and TI for the information, I am afraid that it is a little discrepancy, it's not? 

    I'll try to re-consider all the matter, because I like to be a master of my design and I'm not stopping just because an experimental change in the values of the Type III feedback network brings the circuit to operate well.

    But without the CCM-DCM symbol with its correct PWMVM SPICE model I go nowhere!

    Hoping in some more accurate information, my best regards

    Maurizio

  • Hello Maruizio,

    1. The minimum and maximum voltages on the COMP pin is the maximum voltage you can use from the ramp, so the ramp is about 2A.

    2. and 3. I recommend to switch to pSpice from TI. https://www.ti.com/tool/PSPICE-FOR-TI

    According the CCM-DCM model: If you stabilize a converter for CCM, normally it is stable for DCM as well. So a CCM model is often good enough.

    Best regards,
    Brigitte

  • Thanks a lot....

    About the modulator ramp of the TPS43000, I have found yesterday in another literature, the SLVA301 that it is 1 V.

    So, due the COMP output can arrive at 2 V, what is the suggestion for the maximum gain to avoid saturations with subsequent dazzling of the feedback signal? 

    There is any rule about this?

    About CCM vs. DCM I agree with your assumption while, about PSPICE, I cannot use the TI PSPICE because the CADENCE SW doesn't work anymore (and it was a nightmare to restore it!).

    Thanks again

    Maurizio 

  • Hello Maurizio,

    1V should be a good starting point to not get into saturation, I think.

    For TI Spice, I am sorry that you have issues with it. Normally TI Spice and Cadence should be able to work in parallel without any problems.

    If you are using Cadence, you can use our models in pSpice as well and do not need to use TI Spice.

    Best regards,
    Brigitte