TIDA-050038: Understanding part of the schematic

adevries

Part Number: TIDA-050038

Hello TI Forum,

I am considering using TI's 2 chip solution to power the NXP i.MX 8M Mini. I have been studying the TIDA-050038 schematic to learn how to implement these PMICs in my design, and I do not understand part of the schematic. On sheet 10 of the design (image below), the signal WDOG_B is connected to the base of a PNP transistor (Q3), with the emitted connector to ground. When WDOG_B is high, Q3 will be in reverse-active mode, which I have never seen before. Can anyone explain the purpose of Q3 and Q4? And the design intention behind it?

Thanks

over 3 years ago

0 Layne J over 3 years ago

TI__Genius 12735 points

Hello,

I have forwarded this question to the experts for these parts, please allow a delay in their response until Monday.

Best regards,

Layne J

0 adevries over 3 years ago in reply to Layne J

Intellectual 945 points

Thank you!

+1 Tomi Koskela over 3 years ago

TI__Genius 11020 points

Hello Adevries,

I don't know all the details and design targets for this system, but it seems that the intention is that either POR_B and WDOG_B could control the PMIC_ON_REQ. So in case of POR/WDOG fault the PMIC_ON_REQ would be pulled low to disable the power. However the implementation with the transistors does look little strange, I agree.

Hope this helps.

Thanks.

Regards,

Tomi Koskela

0 adevries over 3 years ago in reply to Tomi Koskela

Intellectual 945 points

Hi Tomi,

Thanks, that does help. Just wanted to make sure I wasn't missing anything!

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TIDA-050038: Understanding part of the schematic