TPS65295: SLP_S4 and VTT_CNTL pin usage when supporting only S0 and S5/S4 states

Hi James

Yuchang will reply to you after his business trip. Thanks!

BR

Ruby

Hi James,

If you don’t need to follow JEDEC power off timing requirements. The two signals can be tied together with one control signal.

Yuchang

Hi Yuchang,

Thanks very much for your reply. Can you please share your understanding of the JEDEC power off timing requirements? I could not find any mention of power off timing requirements in the JEDEC specification. From the timing diagrams in the datasheet, it seems like the shutoff must ensure that VTT disables before *or* at the same time that VDDQ disables, but I'm not sure if this is the only requirement.

Thanks,

James

Hi James,

From my understanding, in the previous validation of the device, the SLP_S4 and VTT_CNTL can be shorted for operation.

Yuchang is responsible for this device so you could double confirm with him about the details and the standard. He is on business trip now, so maybe his feedback has a little delay. 

Thanks,

Andrew

James,

As Andrew said this part was validated some test for both control signals tied together. no issue was found.

I double checked seems there is no power off requirement in JEDEC, maybe the sequence block is from other vendor request, like intel...

let me double check with team and try to feedback this week.

Yuchang

Thank you very much for looking into this Yuchang. To my knowledge, the S4/S5 states are defined by the ACPI standard, which some manufacturers - including Intel - follow for their chips. But I don't think it's required for DDR4 per JEDEC, although I will await your confirmation.

Hi James,

Thanks for your information. Yuchang will double check and feedback to you.

Thanks,

Lishuang

James,

I checked exactly the timing in datasheet is from intel design guide, I agree with you. You can just follow JEDEC spec if your system is not intel platform, don’t need meet the timing picture.

Yuchang