This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28780: ACF controller, OPP problem

Part Number: UCC28780
Other Parts Discussed in Thread: UCC27712

Hello, TI experts! 

I am designing an ACF converter based on UCC28780 and UCC27712.It was supposed to make a converter for an output voltage of 24 V, a maximum power of 80 watts.

I ran into an error triggering problem, presumably OPP.

RM8 (TDK) is used as the transformer core, namely B65811J0250A087, winding 20: 5: 5. The problem is that I observe the saturation of this core at a switching frequency of 2 kHz, which is why I suppose the OPP is triggered.

How can this problem be solved? Or is this considered normal operation?
Also the UCC27712 fails often, I get LO of no more than 2.25 volts.

Thanks in advance for your answer!

If necessary, I am ready to provide a schematic and a design calculator.

  • Hello Nikita, 

    Thank you for your interest in the UCC28780 ACF controller. 
    Certainly, a saturating core is not normal operation. 

    Based on the catalog number the core property of AL = 230nH/T^2 at 20T yields 100uH, which is "in the right ball park". 
    This should be a gapped core and should not be saturating.  Please examine your transformers to verify that the cores are indeed gapped. 

    Another possibility is that you may have excessive delay in your current sense path, that allows much higher peak current than you expect. 
    Please check the values of Ropp and Ccs to ensure that their time constant is less than 100ns.  It should not require filtering much higher than this.  

    The UCC27712 failures might be the result of excess dv/dt during the lower MOSFET turn-off transition.  If the core is near saturation the current is rising to a very high level, it can drive the dv/dt of the switched node higher than the UCC27712 can withstand.  Also, make sure that the VDD voltage on the UCC27712 is 17V or less.  The part is more susceptible to high dv/dt when VDD is > 17V.

    Finally, the switching frequency should not be as low as 2kHz.  Is this a typo (should be 200kHz)? Or are you referring to the burst frequency in low power SBP mode?  Cycle-by-cycle switching at 2kHz does not make sense.  Please recheck this operation.


  • Yes, I mean, cycle-by-cycle switching to 2kHz in power-saving mode, at the very beginning of turning on the controller.
    I will double-check the switching frequency.

    Many thanks for your help!

  • Hello Nikita,

    Thank you for verifying the 2kHz operation.  Because this happens at the very beginning of turn-on, it is now a very likely to be normal operation.  This low frequency happens when the output voltage is very near zero, as at initial start-up.  At this time, the reflected voltage is very low and the demagnetization time is extended very long.  It is entirely likely to be around 2kHz for  a short time.  As Vout increases, the demag time becomes shorter and switching frequency increases.  Once at regulation, the switching frequency should be in the 100's of kHz.

    There is no mode called "power-saving" mode.  I cannot correlate it to any normal mode of the controller. A the beginning of start-up, there is Start Mode 1 and Start Mode 2 (SM1, SM2) and then AAM until Vout regulation is achieved. If the transformer is saturating during these modes, then the cause of that saturation must be determined and fixed.  I provided two possibilities to be checked: no gap or gap too small, or excessive filtering on CS.  Please check these possibilities. 

    To account for UCC27712 failures, I suggested to check on excessive dv/dt or VCC1 higher than 17V.  I still recommend to check this.

    I reread your description of the LO output. If it only rises to 2.5V each cycle, what is the VCC2 value?  What kind of loading is on the LO pin?
    I'll probably need to review the schematic diagram.  And waveforms of LO, Vds of the low-side switch, and the transformer primary current will also be helpful.      


  • SBP mode you specified correctly. I apologize for the inaccuracy.

    I will make sure to check the gaps to make sure they are correct.
    Ropp = 2 kΩ, Ccs = 6 pF for CS filtering.

    The supply voltage of the UCC27712 at the start of ACF operation is 17.5 V, which corresponds to the UCC28780 turn-on threshold. At LO = 2.25 V, the supply voltage VDD2 is in the range of 16-17.5 V.

    I attach the schematic diagram. At the moment I can not provide you with the requested waveforms, as I expect new UCC27712.

    I will definitely provide you with the waveforms for analysis as soon as the UCC27712 is delivered to me.

  • There is a mistake in the circuit attached above, I use a Zener diode BZX384-C18,115 on the board to power VDD2.

  • Hello Nikita,

    Thank you for providing the schematic diagram. I see a few items that can be improved, but nothing that accounts for 2.25V on LO.

    I suggest that you check the actual value of R23, which is shown as15K. If its actual value is 15ohms, then that will overload the LO output and can account for the 2.25V that you are measuring.  The wrong value for R23 may have been accidentally installed.  Also check the high-side R22 for the same possible mistake.

    For possible causes of transformer saturation, I suggest to review the transformer flux density calculation and compare to the core material rating for Bsat at the operating temperature.  In an 80W design, 20T on an RM8 core may not leave enough margin to saturation.
    Your choice of Ropp and Ccs (R21 & C32) values seem to be okay... no excessive time delay for VT3 turn-off.   

    The current sense resistor R31 = 0.127ohm will allow 0.8V/0.127R = 6.3Apk.  This seems very high, so this may be the cause of the saturation. Bmax = Lm*Ipk/(Np*Ae).  Please recheck your calculation for R31, then decide if RM8 core is the right core size for your application, or if you need more turns on the primary winding to reduce Bmax. 

    For circuit improvements, I recommend:
    1.  Remove C48 (3.3pF) from the VS pin.  There should be no capacitance on the VS input.  Even stray PCB capacitance should be minimized.
    2.  Remove C38 (10nF) from the FB pin. This cap is unnecessary and adds undesirable delay to the feedback loop.
    3.  Replace R10 (10R) with a linear regulator (LDO or MOSFET with gate Zener) to drop +V_AUX down to ~17V.  Since +V_AUX will be about ~24V, the current through R10 and 18V Zener VD? will be 6V?10R = 600mA.  This will overheat bot R10 and VD?.  Use a linear regulator to allow the driver load to determine how much current is pulled from +V_AUX. The bias loss will be much less.  
    4.  Increase R16 from 150K to 1Meg, to reduce loading on HVG output.  150K is not bad, but just not necessary to be that low.   
    5.  While L5 needs to be a power inductor, it is not necessary for L4 to be a power inductor.  L4 is a damping inductance across L5, but carries much less current.  Both L4 and R56 could be combined into a single 1206-sized (EIA) inductor.  However, for test and debug purposes the existing components can be used. Later you can reevaluate to reduce cost and size.
    6.  Once the system is operational, check the temperature rise of VT3.  280mR may not be low enough for the rms current flowing through it at 80W output.
    7.  RK1 will limit inrush current as expected, however it will also contribute constant loss at full power.  This will reduce the full-load efficiency that you may be expecting from the ACF topology.  The same can be said for RK3 on the output.  Consider removing them.
    8.  If you make any changes to the power components (different MOSFET, different Lm or turns ratios), please run the numbers through the UCC28780 Calculator Tool again to determine updated values for RDM and RTZ, and other components.  It is important that those two resistors are set to values that correctly match the parameters of the power stage, or sub-optimal performance may result.