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TPS7A85A: Input voltage ripple

Mia Ma
Intellectual 1915 points
Part Number: TPS7A85A
Other Parts Discussed in Thread: TPS7A85,

Hi team,

My customer is evaluating our TPS7A85, SCH and PCB are as attached files.

And here is a condition which is confusing for us. My customer is testing this with a digital power input.

There will be a Vin ripple and Bias pin ripple could be measured which is worst especially while use Bias supply, the ripple peak-peak value could be 178mv.

so want to confirm with you about this condition, if the ripple is reasonable, could you help with this case.

Thanks.

Best regards

Mia Ma

TPS7A85 ripple.7z

  • 0
    TI__Genius 12040 points

    Hi Mia,

               Given that the VIN in your schematic is less than 1.4V, you will have to use VBIAS. With VBIAS, as you mention, the peak to peak ripple in VIN is 178mV (lets assume 200mV). This implies that the Input voltage varies between 1.25V and 1.45V (with an average value of 1.35V). Since Vout is 1V and the Min value of Vin is 1.25V, the minimum input-output differential is 250mV. The EC table in the datasheet suggests that the maximum value of the dropout is 240mV, but typically 150mV of dropout is sufficient to maintain regulation when VBIAS is used (Fig 24 of the datasheet also suggests this). To me, this implies that the LDO has just about sufficient Input-Output headroom to maintain regulation even at min VIN. You will probably see a ripple in the output voltage, reduced in amplitude by PSRR when compared to Vin. Hope this has answered your query.

    Regards,

    Srikanth

          

  • 0 in reply to Srikanth Lolla Venkata
    TI__Intellectual 1915 points

    Hi Srikanth,

    Thanks for your support here.

    As you mentioned, this large ripple may lead to wrong output as dropout margin.

    But we are wondering why there is such a large ripple existing at IN side, the signal is right come from the digital power, if the TPS7A85A work leading to this?  And if eventhough withiout bias working, there will be a 80mv ripple at IN which is not regular shape.

    By the way, customer has already tried larger ceramic cap here which is not helpful.

    If there is not such a large ripple, the dropout risk will be removed.

    Thanks

    Best regards

    Mia Ma

  • 0 in reply to Mia Ma
    TI__Genius 12040 points

    Hi Mia,

               At this point I don't think the LDO is causing the ripple at VIN. I will will look into it a bit more and get back to you on Tuesday.

    Regards,

    Srikanth

  • 0 in reply to Srikanth Lolla Venkata
    TI__Intellectual 1915 points

    Hi Srikanth，

    Thanks a lot, look for your comments here.

    Best regards

    Mia

  • 0 in reply to Mia Ma
    TI__Genius 12040 points

    Hi Mia,

              Could you also provide me the screenshot of VOUT pin? Just to clarify, even with 200mV of peak to peak ripple in VIN it looks you have sufficient headroom to maintain regulation at 1V and not enter dropout. Do you see this ripple if the enable signal is removed from the LDO? Thanks!

    Regards,

    Srikanth

  • 0 in reply to Srikanth Lolla Venkata
    TI__Intellectual 1915 points

    Hi Sriikanth,

    Thanks for your suggestion here, Customer is gathering the waveform and confirmming EN removed status. I will update with when they done, and I may directly connect with through email.

    Thanks.

    Best regards

    Mia Ma

  • 0 in reply to Mia Ma
    TI__Genius 12040 points

    Hi Mia,

               Sure, you can directly email me. 

    Regards,

    Srikanth