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UCC24624: MOSFET selection

Hong Sheng Chong
Prodigy 20 points
Part Number: UCC24624
Other Parts Discussed in Thread: TIDA-010081, TIDA-010080

Hi experts, 

In the datasheet, section 9.2.2.1, "Generally, the on-state resistance must be selected so that the 35-mV proportional gate drive threshold doesn't get activated until last 25% of the overall conduction time."

Here is my question, due to my LLC converter maximum output current is 50 A, and almost all the available MOSFET that can be chosen come with Rds_on far larger than the recommended value. So I am asking what if the Rds_on of the implemented MOSFET is far larger? And if I choose to parallel the MOSFET will Rds_on be equally divided? 

Thanks

  • 0
    TI__Mastermind 26770 points

    Hello Hong Sheng,

    Thank you for your interest in the UCC24624 SR controller.

    Yes, in such cases of high current it is common to use parallel MOSFETs to achieve the lower equivalent Rds(on).  These MOSFETs will shar the current nearly equally, since Rds(on) has a positive temperature coefficient, each FET's Rds(on) value increases as it gets hotter. Then current prefers to flow though the lower Rds(on) FET which raises its temperature.  As long as the parallel FETs have approximately the same junction temperature, their Rds(on)s will also be approximately equal.

    When large MOSFETs are paralleled, their total gate charge also increases proportionately.  All of this charge is processed through the SR controller, so be careful to consider the junction temperature of the SR controller.  If possible, use a dropping resistor in series with VDD to bring VDD down to 9~12V to minimize the loss within the SR controller.  Lower Vgs means lower gate charge and lower average SR bias current.  But if Vgs is set too low, then the Rds(on) will go up and SR FET losses will rise, so there may be a tradeoff to be made.  Larger pads on the SR controller pins or a heat-sink glued to the top can help dissipate the heat.  

    Regards,

    Ulrich

  • 0 in reply to Ulrich Goerke
    Prodigy 20 points

    Thanks, it helps me a lot. But there are other issues remained.

    [First Question]

    According to the datasheet, section 9.2.2.1, "Generally, the on-state resistance must be selected so that the 35-mV proportional gate drive threshold doesn't get activated until last 25% of the overall conduction time."

    From the provided equation, the calculated recommended Rds(on) is 0.63mOhm (Iout(max)in my project is 50A).

    But I can't find any MOSFET with a Rds(on) smaller than 0.63mOhm. Furthermore, those FETs with Ids(max) > 50A has a far more larger Rds(on). if wanna satisfy the recommended Rds(on) value, I have to parallel 10+ FETs at/ the same time.
    In addition, in Design Guide: TIDA-010080 and TIDA-010081, the LLC secondary MOSFET selection design didn't consider the recommended Rds(on) equation.


    So, I am wondering, what if my equivalent Rds(on) of FETs are higher than the recommended value? Is this Rds(on) recommended value very important in MOSFET selection and implementation?

    [Second Question]

    I am planning to use the GaN HEMT devices. But as i know, although the GaN HEMT didn't have parallel diode, it can conduct as a parallel reverse diode when synchronous when Vgs =0 and Vds< Vgs(th). So, it is alike to the SiC or Si MOSFET. But maybe there are some different in the soft-start stage or before VCC is powered.
    So, I am wondering, is there possible to implement GaN HEMT with UCC24624 in LLC synchronous application?

    Thanks

  • +1 in reply to Hong Sheng Chong
    TI__Mastermind 26770 points

    Hello Hong Sheng,

    I think that in the case of a very high current output such as 50A, it is impractical to meet the Rds(on) criterion at the  peak current.
    With LLC, the current follows a sinusoid down form the peak, so eventually the current will drop to a point where the Vds will drop below 35mV.  At this point, the proportional gate drive will drop Vgs in order to regulate Vds to 35mV. 
    This will probably happen very close to the end of the conduction interval (maybe the last 5%), but at least Vgs will start to drop and turn-off should be fast.

    Maybe 10+ MOSFETs in parallel is also impractical, but you may need more than 2 in parallel.  Keep track of the total gate charge that must be driven through the SR controller.  If it is too much and the driver can overheat, then an emitter-follower buffer (NPN+PNP) can be used to relieve the controller of most of the gate charge, and still keep Vgs controlled proportionally.

    I don't know if a GaN FET can be driven directly by the UCC24624.  If the GaN's Vgs characteristic is similar to that of a Si FET, then I see no reason why it wouldn't work.

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Prodigy 20 points

    Thanks a lot!

    last question, what should I consider when I am using UCC24624 with SiC MOSFET?

    Thanks!

  • 0 in reply to Hong Sheng Chong
    TI__Mastermind 26770 points

    Hello Hong Sheng,

    From what I understand, SiC MOSFETs require Vgs close to 15V to turn on fully, and Vgs = -3V to turn off securely.
    The UCC24624 clamps its output voltage to ~11V (because it is optimized for Si Fets) which will probably not enhance SiC FETs enough.  
    Also, it cannot generate negative gate drive. 

    You may need to design or interface a special SiC driver between the UCC24624 and the MOSFET.

    Regards,
    Ulrich