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TPS3840-Q1: Question about nReset pin behavior at slow VDD start up

Part Number: TPS3840-Q1
Other Parts Discussed in Thread: TPS3840

Hello team,

I have a question about RESET pin behavior

If the VDD slew rate is very slow and the slew rate is longer than Tstrt+Td, What is the behavior of nRESET?

I guess the behavior will be either ① or ②. Which one is correct?

①Regardless of the VDD voltage , the nRESET will become High after Tstrt+Td. When the VDD decrease lower than VIT-, the nRESET will become Low.

②nRESET will be stay Low. Once the VDD reaches VIT+ and pass Td, the nRESET become High.


Yuta Kurimoto

  • Hi Yuta-san,

    Option #2 is correct.  There are internal circuits that are defined when VDD >= VDD min voltage.  When VDD reaches to VDD min level, the internal circuits will allow tstrt time to begin.  Therefore, tstrt is defined from the point where VDD crosses VDD min level.  The picture in the TPS3840 datasheet is a little misleading.  The pic below is a better representation of tstrt when VDD crosses the VDD min level.


    Please note that when VDD < VPOR, the output (/RESET) will follow VDD until VDD cross the VPOR threshold.  Once cross, the output (/RESET) will be high after VDD reaches VIT+.  See below figure for a better explanation.

    I hope I have answered your questions.  If there are no other questions, please click on "resolved" to close the thread.  Thank you!


  • Hi Yuta-san,

    Glad to be of help!  Thank you and good luck to you!