CSD18537NQ5A: Buck Converter high drive FET(6nSec) pulse exceeds VDS rating

Hi Jojo,

Thanks for your interest in TI FETs. There is a risk of damage to or failure of the device any time the absolute maximum ratings are exceeded. The pulse width is short but there is significant ringing on the waveform. How and where are you making the measurement? The scope probe should be as close as possible to the FET pins with a very short ground connection. Please visit our Support & training page where you will find an app note on ringing reduction in sync buck converters. Please let me know if you need further assistance.

Best Regards,

John Wallace

TI FET Applications

Hi Jojo,

Following up to see if this resolved your issue. Please let me know if I can be of further assistance. If I don't hear back from you, I will assume your issue has been resolved and will close out this thread.

Thanks,

John

Hi John,

Hi John,

Hi John,  It does clarified our question.  1)What's the next FET CSD or closest series with higher VDS rating? 2) In what condition or scenario that a "shoot- through" event could happen on this configuration. It it's possible how to prevent it?

Hi Jojo,

Thanks for the additional information. The CSD18537NQ5A is a 60V FET. TI also makes 80V and 100V devices in the same 5x6mm SON package. The two closest FETs in on resistance to CSD18537Q5A are the CSD19534Q5A (15.1mOhm vs. 13mOhm at VGS = 10V) and CSD19533Q5A (9.5mOhm on resistance at VGS =10V). Based on the phase node waveform in your earlier post, the low side FET is seeing excess VDS. It is also a 60V FET and the 100V FET is the CSD19531Q5A (6.4mOhm vs. 6.8mOhm).

The waveform shows the input voltage is around 30V. Normally, this would require a 40V or 60V FET but the overshoot at turn-on is more than 2x the input voltage. I am surprised at the excess switch node ringing. What are the conditions for the waveform you shared? What are your requirements: Vin, Vout and Iout? It looks like there is a R-C snubber at the switch node. Have you tried adjusting the values to reduce the ringing? You can also adjust the value of R89 to slow down turn on of the high side FET. Is it possible to add a series gate resistor for the high side FET?

The TPS40170 controller should have adequate shoot-thru protection and the FETs are optimized to prevent false turn-on due to CdV/dt induced voltage on their gates. It is more likely that the low side FET is going into avalanche when exceeding BVDSS. The waveform does not show any clipping at the peak probably because the pulse width is so short. TI rates our FETs for single pulse avalanche - not repetitive avalanche.

Thanks,

John

Hi Jojo,

Just checking in to see if your issue has been resolved. Please let me know.

Thanks,

John