My customer is using our TPS7A9101DSKR . From the timing diagram for this DCDC is as below.
They would like to know why does the out voltage ramp up before EN triggers and how to improve it? Thanks.
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I could not find anything on this in our archives, so I tested an EVM and this is not happening on the EVM either. The issue is something in the system this linear regulator is installed onto. I would first make sure there are no leakage paths in the design, by ensuring that the board is thoroughly cleaned. I would also review what leakage paths may exist on the output which may inadvertently pull up the LDO output before it is enabled.
Channel 1 = Green = Vin = 4V
Channel 2 = Blue = Vout
Channel 3 = Yellow = Ven = 4Vpk
Same plot but much more zoomed in to confirm Vout does not rise prematurely.