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TPS7H4010-SEP: Designing with TPS7H4010

Shibin Varghese
Prodigy 185 points
Part Number: TPS7H4010-SEP

Hi Team, 
I am designing a buck converter with TPS7H4010.
In the datasheet, it is mentioned the VCC pin should not be loaded. 
I want to run the device in constant frequency. So I need to pull the SYNC/MODE pin high.
The maximum recommended voltage at the SYNC/MODE pin is 5.5V.
1). TPS7H4010 is the only power supply in the system. So can I connect VCC to SYNC/MODE pin?.
My required output voltage is 3.6V and my input is 20V.
The maximum load current is less than 500mA. 
The value of Rfbt is taken as 100K and the calculated value for Rfbb is 38.78K.
The inductor value is chosen to be 4.7uH and the Cout is nearly 100uF.
2) Is my calculation correct?.
3). What should be the value of the feed-forward capacitor in my design?.
4). Also, How to calculate a proper value for Cff?.
5). Is it ok to let the PGOOD pin floating?.
6). What is the maximum output current if internal LDO?.
7). The BIAS pin is connected from the 3.6V out.


  • 0
    TI__Guru 62930 points

    Good Morning.

    The engineer that supports this device is out of the office today.  You can expect a reply on Monday.

    I apologize for the delay.

    Regards,

    Wade

  • 0
    TI__Expert 7055 points

    Hi Shibin,

     

    Thanks for your patience. I will need a little more time to review the rest of your questions, but here are the answers I can provide now:

     

    1. Yes, you can connect VCC pin to bias the SYNC/MODE pin. In fact, this is what we do on the EVM. You can see this in the board schematic shown in the in the EVM User's guide. 
    2. Yes, it is.
    3. I will return to this question.
    4. I will return to this question.
    5. In theory, this open drain pin can be left floating but I would want to check with our design team first to confirm there are no issues and that this signal is not used internally for other purposes such as test modes. Regardless of whether this pin can be left floating, all testing and characterization (including TID and SEE radiation testing) has included a pullup resistor to bias this circuit. If possible, I would recommend a pullup even if you don't use the PGOOD signal provided.
    6. I will return to this question, but in the meantime can you clarify the reason you are asking? I’m not sure if this is what you were planning, but loads should not be placed on this pin.
    7. Yes, this is ok. According to the datasheet, "TI recommends tying to VOUT when 3.3 V ≤ VOUT ≤ 18 V, or tie to an external 3.3-V or 5-V rail if available, to improve efficiency"

    Thanks,

    Sarah

  • +1 in reply to Sarah Koch
    Prodigy 185 points

    Hi Sarah,
    Thank you for your reply.
    I'm not planning to load the VCC pin. I just want to confirm connecting VCC with SYNC/Mode pin won't affect the performance of the device. Thank you for your support.
    Please update the rest of the answers.

  • +1
    TI__Expert 7055 points

    Hi Shibin,

    Here are the answers to your remaining questions (3 & 4) about the feed-forward capacitor:

    Since you're using R FBT ≤ 100 kΩ it is unlikely that you will need Cff unless COUT is mainly ceramic low-ESR capacitors.

    The ESR from COUT is often large enough to provide a zero ( fZ-ESR = 1 / (2π × ESR × COUT) ) at a low enough frequency to boost the phase at the crossover frequency. However, if the ESR of your COUT is not large enough to provide the needed phase boost, Equations 21 and 18 from section 7.3.10 of the datasheet can be used as a guide for selecting an appropriate value for Cff. This section of the datasheet includes a few other details on Cff that may be useful if your design requires it.

    Thanks,

    Sarah