My customer is working on a DDR3L power supply design that will use the TPS51916.
We have come up with some questions:
- They have been mostly using Webench as a basis for the design, and had a question on the implementation of the Cvttref. Mainly, it is a 220nF COG/NP0 Class-1 capacitor, and there are no selections within Webench that are class 2 (X5R to X7R or so). This particular combination of cap value and cap class make for a limited number of products available, and the ones that are available are quite large in size (1206 is the smallest). Is there a very specific reason for having a Class-1 cap on this output, or can we have a higher capacitance Class-2 cap that would have a guaranteed minimum capacitance of .22uF based on deratings of DC bias and Temperature? Would the varying capacitance value over temperature cause a problem?
- Can we get some clarification on the best operating modes between the D-CAP and D-CAP2? It would appear that the D-CAP will have a better operation with regards to transient response. Is there any reason to consider the D-CAP2 aside from a desire to keep with MLCCs?
- We are a bit curious on how the transient response is better at lower switching frequencies… The general rule we have assumed is the bandwidth is about 10% of the switching frequency… It would seem that raising the switching frequency would raise the control bandwidth… Is that not the case for this supply, and that general rule does not apply?